Peripheral Interface: Difference between revisions
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(Added more info about PI domains.) |
Mazamars312 (talk | contribs) (Timing counter sizes) |
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-n = Default value n at power on |
-n = Default value n at power on |
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[x:y] = Specifies bits x to y, inclusively</pre> |
[x:y] = Specifies bits x to y, inclusively</pre> |
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==== <span style="display:none;">0x0460 0000 - PI_DRAM_ADDR |
==== <span style="display:none;">0x0460 0000 - PI_DRAM_ADDR ==== |
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---- |
---- |
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{{#invoke:Register table|head|550px|PI_DRAM_ADDR <code>0x0460 0000</code>}} |
{{#invoke:Register table|head|550px|PI_DRAM_ADDR <code>0x0460 0000</code>}} |
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32'h0460_002C |
32'h0460_002C |
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|R/W |
|R/W |
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|This is a |
|This is a 4 bit counter for the timing on how many concurrent reads or writes can happen after 128 bytes of data are process and then the Cart bus has to advise to the Cart an update address. |
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Default value set by games is ( |
Default value set by games is (4'h07) |
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|PI_BSD_DOM1_RLS_REG |
|PI_BSD_DOM1_RLS_REG |
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32'h0460_0030 |
32'h0460_0030 |
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|R/W |
|R/W |
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|This is a |
|This is a 2 bit counter for the timing on how long the Read or Write signal is to stay HIGH before it can go LOW. |
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This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOMX_LAT_REG. |
This counter runs after the PI_BSD_DOMX_RLS_REG counter and increases by 1 every clock cycle of the RCP (62.5mhz). Once the counter reaches this value, the process will go to idle or back to PI_BSD_DOMX_LAT_REG. |
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Default value set by games is ( |
Default value set by games is (2'h3) |
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