Peripheral Interface: Difference between revisions
Clarify more behavior of PI_BB_RD_LEN and PI_BB_WR_LEN
(PI_BB_RD_LEN, PI_BB_WR_LEN) |
(Clarify more behavior of PI_BB_RD_LEN and PI_BB_WR_LEN) |
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Line 416:
'''Extra Details'''
: It is currently unknown what the behavior is if a DMA extends out of the bounds of the target PI Buffer, and whether both buffers can be accessed in one transfer.▼
: The busy bits in '''PI_STATUS''' also applies to these transfers.
▲It is currently unknown what the behavior is if a DMA extends out of the bounds of the target PI Buffer, and whether both buffers can be accessed in one transfer.
: These transfers also trigger an interrupt upon completion. It is the same interrupt used for regular PI DMAs.
==== <span style="display:none;">0x0460 005C - PI_BB_WR_LEN</code> ====
Line 444 ⟶ 445:
'''Extra Details'''
: It is currently unknown what the behavior is if a DMA extends out of the bounds of the target PI Buffer, and whether both buffers can be accessed in one transfer.▼
: The busy bits in '''PI_STATUS''' also applies to these transfers.
▲It is currently unknown what the behavior is if a DMA extends out of the bounds of the target PI Buffer, and whether both buffers can be accessed in one transfer.
: These transfers also trigger an interrupt upon completion. It is the same interrupt used for regular PI DMAs.
==== <span style="display:none;">0x0460 0070 - PI_BB_NAND_ADDR</code> ====
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