The MIPS Interface (or MI) is one of multiple I/O interfaces in the RCP. It is the interface between the RCP and the VR4300 CPU, primarily used for enabling/disabling interrupts and checking their status.
Memory mapped registers are used to configure the MIPS Interface. The base address for these registers is 0x0430 0000, also known as MI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add 0xA000 0000 to the address. As an example, to directly write to the MI_MODE register, use address 0xA430 0000.
Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. Behavior is unknown when writing 1's to both Set and Clear bits in a pair at the same time.
Registers
Table Notation:
R = Readable bit
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively
0x0430 0000 - MI_MODE
MI_MODE 0x0430 0000
|
| 31:24
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 23:16
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 15:8
|
U-0 |
U-0 |
W-0 |
W-0 |
W-0 |
W-0 |
RW-0 |
RW-0
|
| — |
— |
Details Below
|
| 7:0
|
RW-0 |
RW-0 |
RW-0 |
RW-0 |
RW-0 |
U-0 |
RW-0 |
RW-0
|
| Details Below |
INIT_LENGTH[6:0]
|
READ: WRITE:
[13] — [13] Set RDRAM register mode
[12] — [12] Clear RDRAM register mode
[11] — [11] Clear DP interrupt
[10] — [10] Set ebus test mode
[9] RDRAM register mode [9] Clear ebus test mode
[8] ebus test mode [8] Set init mode
[7] init mode [7] Clear init mode
[6:0] init length [6:0] init length
0x0430 0004 - MI_VERSION
MI_VERSION 0x0430 0004
|
| 31:24
|
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-? |
R-?
|
| RSP_VERSION[7:0]
|
| 23:16
|
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-? |
R-?
|
| RDP_VERSION[7:0]
|
| 15:8
|
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-? |
R-?
|
| RAC_VERSION[7:0]
|
| 7:0
|
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-? |
R-?
|
| IO_VERSION[7:0]
|
| bit 31-24 |
RSP_VERSION[7:0]: RSP hardware version
|
| bit 23-16 |
RDP_VERSION[7:0]: RDP hardware version
|
| bit 15-8 |
RAC_VERSION[7:0]: RAC hardware version
|
| bit 7-0 |
IO_VERSION[7:0]: IO hardware version
|
Extra Details:
- It is not known for certain what values could exist here. Variations seen across source documents and emulators include
0x0101_0101, 0x0202_0102, and 0x0201_0202. Testing should be performed on all revisions of the N64 motherboard and development systems. Results will be listed here.
0x0430 0008 - MI_INTERRUPT
MI_INTERRUPT 0x0430 0008
|
| 31:24
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 23:16
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 15:8
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 7:0
|
U-0 |
U-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0 |
R-0
|
| — |
— |
DP |
PI |
VI |
AI |
SI |
SP
|
| bit 31-6 |
Undefined: Initialized to 0
|
| bit 5 |
DP: Interrupt flag - Set when a full sync completes
|
| bit 4 |
PI: Interrupt flag - Set when a PI DMA finishes
|
| bit 3 |
VI: Interrupt flag - Set when VI_V_CURRENT == VI_V_INTR
|
| bit 2 |
AI: Interrupt flag - Set when no more samples remain in an audio stream
|
| bit 1 |
SI: Interrupt flag - Set when a SI DMA to/from PIF RAM finishes
|
| bit 0 |
SP: Interrupt flag
|
0x0430 000C - MI_MASK
MI_MASK 0x0430 000C
|
| 31:24
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 23:16
|
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0 |
U-0
|
| — |
— |
— |
— |
— |
— |
— |
—
|
| 15:8
|
U-0 |
U-0 |
U-0 |
U-0 |
W-0 |
W-0 |
W-0 |
W-0
|
| — |
— |
— |
— |
Details Below
|
| 7:0
|
W-0 |
W-0 |
RW-0 |
RW-0 |
RW-0 |
U-0 |
RW-0 |
RW-0
|
| Details Below
|
READ: WRITE:
[11] — [11] Set DP Interrupt Mask
[10] — [10] Clear DP Interrupt Mask
[9] — [9] Set PI Interrupt Mask
[8] — [8] Clear PI Interrupt Mask
[7] — [7] Set VI Interrupt Mask
[6] — [6] Clear VI Interrupt Mask
[5] DP Interrupt Mask [5] Set AI Interrupt Mask
[4] PI Interrupt Mask [4] Clear AI Interrupt Mask
[3] VI Interrupt Mask [3] Set SI Interrupt Mask
[2] AI Interrupt Mask [2] Clear SI Interrupt Mask
[1] SI Interrupt Mask [1] Set SP Interrupt Mask
[0] SP Interrupt Mask [0] Clear SP Interrupt Mask