MIPS Interface: Difference between revisions
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Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. Behavior is unknown when writing 1's to both Set and Clear bits in a pair at the same time. |
Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. Behavior is unknown when writing 1's to both Set and Clear bits in a pair at the same time. |
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Accesses beyond <code>0x0430 0010</code> are mirrored, so only the first four bits are taken into account for address decoding. |
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= Registers = |
= Registers = |
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