MIPS Interface: Difference between revisions
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(Asserting both set and clear bits in the same write results in no effect.) |
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[1] SI Interrupt Mask [1] Set SP Interrupt Mask |
[1] SI Interrupt Mask [1] Set SP Interrupt Mask |
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[0] SP Interrupt Mask [0] Clear SP Interrupt Mask |
[0] SP Interrupt Mask [0] Clear SP Interrupt Mask |
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</pre>Notice that disabling an interrupt does not prevent the interrupt to be raised in MI_INTERRUPT. It just prevents the interrupt to be signaled to the CPU. If a mask is enabled while the respective interrupt is already set in MI_INTERRUPT, the interrupt is signaled to the CPU right away. |
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