MIPS Interface: Difference between revisions

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Memory mapped registers are used to configure the MIPS Interface. The base address for these registers is <code>0x0430 0000</code>, also known as MI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add <code>0xA000 0000</code> to the address. As an example, to directly write to the MI_MODE register, use address <code>0xA430 0000</code>.

Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. ~~Behavior is unknown when~~ writing 1's to both Set and Clear bits in a pair at the same time.

Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. When writing 1's to both Set and Clear bits in a pair at the same time results in no effect, the previous state is preserved.

Accesses beyond <code>0x0430 0010</code> are mirrored, so only the ~~first~~ four bits are taken into account for address decoding.

Accesses beyond <code>0x0430 0010</code> are mirrored, so only the least significant four bits are taken into account for address decoding.

= Registers =

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 Memory mapped registers are used to configure the MIPS Interface. The base address for these registers is <code>0x0430 0000</code>, also known as MI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add <code>0xA000 0000</code> to the address. As an example, to directly write to the MI_MODE register, use address <code>0xA430 0000</code>.
-Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. Behavior is unknown when writing 1's to both Set and Clear bits in a pair at the same time.
+Note that some of these registers have different behavior when writing to them, than when reading from them. When writing to a register that has Set and Clear bits, write a 1 on the desired bit. Writing 0's have no effect. When writing 1's to both Set and Clear bits in a pair at the same time results in no effect, the previous state is preserved.
-Accesses beyond <code>0x0430 0010</code> are mirrored, so only the first four bits are taken into account for address decoding.
+Accesses beyond <code>0x0430 0010</code> are mirrored, so only the least significant four bits are taken into account for address decoding.
 = Registers =

MIPS Interface: Difference between revisions

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