MIPS Interface: Difference between revisions

| 5 | DP | Interrupt flag - Set when the RDP finishes a full sync (requested explicitly via a SYNC_FULL command)

| 4 | PI | Interrupt flag - Set when a PI DMA transfer finishes

| 3 | VI | Interrupt flag - Set when the VI starts processing a specific half-line of the screen (<code>VI_V_CURRENT {{=}}{{=}} VI_V_INTR</code>). Usually, this is configured with `VI_V_CURRENT = 2` so that it behaves as a VBlank interrupt.

| 2 | AI | Interrupt flag - Set when the AI begins playing back a new audio buffer (to notify that the next one should be enqueued as soon as possible, to avoid crackings)

| 0 | SP | Interrupt flag - Set when the RSP executes a BREAK opcode while SP_STATUS has been configured with the INTERRUPT_ON_BRAK bit; alternatively, it can also be set by explicitly writing the `INTERRUPT` flag in the SP_STATUS register (by either the CPU or the RSP itself).