EverDrive-64 v3
The EverDrive-64 v3 is a flash cart made by Krikzz.
Basic information
ROM: Max 64MiB
RTC: supported
Save: 4k/16k bit EEPROM, 32KiB/128KiB SRAM, 128KiB Flash
USB Serial: 512-bytes block read-write
Registers
All registers must be accessed by 32bit word, but it seems only lower 16bits are valid.
High 16bits of all registers seems REG_STATUS on read.
Base PI address for registers is 0x08040000
(Cartridge Domain 2, SRAM area +0x40000)
You should access these registers from CPU through no-cached segment, i.e. +0xA0000000
, ex. 0xA8040020
for REG_KEY.
PI address | name | R/W | description |
---|---|---|---|
0x08040000 | REG_CFG | R/W | ED64 general configurations |
0x08040004 | REG_STATUS | R | ED64 registers, SPI, DMA statuses |
0x08040008 | REG_DMA_LEN | W | SD/USB DMA length in 512bytes blocks - 1 (ex. 0 = 0x200 bytes) |
0x0804000C | REG_DMA_RAM_ADDR | W | SD/USB Cart address in 2048bytes blocks (ex. 1 = 0x00000800) |
0x08040010 | REG_MSG | ? | ? |
0x08040014 | REG_DMA_CFG | W | Invoke SD/USB DMA |
0x08040018 | REG_SPI | R/W | SPI (SD card) DAT/CMD (write invoke CLK) |
0x0804001C | REG_SPI_CFG | W | SPI (SD card) configurations |
0x08040020 | REG_KEY | W | Enable or disable ED64 registers |
0x08040024 | REG_SAV_CFG | W | Save configurations (EEPROM/SRAM/FLASH) |
0x08040028 | REG_SEC | ? | ? |
0x0804002C | REG_VER | R | Hardware version |
0x08040030 | ? | R/W | I2C to access RTC |
0x08040034 | ? | ? | ? |
0x08040038 | ? | ? | ? |
0x0804003C | ? | ? | ? |
0x08040040 | REG_CFG_CNT | ? | FPGA? |
0x08040044 | REG_CFG_DAT | ? | FPGA? |
0x08040048 | MAX_MSG | R/W | Some configurations |
0x0804004C | REG_CRC | ? | ? |
0x08040050 | ? | ? | Flash? |
0x08040054 | ? | ? | Flash? |
0x08040000 (REG_CFG)
Read/Write
bit from lsb | description |
---|---|
15 | 1=start FPGA configuration?? |
9-8 | D64 specific?? |
6-5 | I2C/RTC?? |
3 | WR_ADDR_MASK?? |
2 | WR_MOD?? |
1 | 1=16bit swap on SD DMA read |
0 | 1=enable SDRAM on cart (usually set to 1) |
0x08040004 (REG_STATUS)
Read only
bit from lsb | description |
---|---|
15 | 1=SDRAM enabled? |
4 | SPI? |
3 | RXF# on USB FIFO (0=some data from Host exists) |
2 | TXE# on USB (0=able to send some data to Host) |
1 | DMATOUT (1=last DMA was timed out, i.e. last transfer is less than 512bytes) |
0 | DMABUSY (1=DMA is ongoing) |
0x08040008 (REG_DMA_LEN)
Write only
bit from lsb | description |
---|---|
15-0 | Next SD/USB DMA transfer size in 512 bytes step, minus 1.
ex. 0 = 0x200 bytes, 1 = 0x400 bytes, 2 = 0x600 bytes... |
0x0804000C (REG_DMA_RAM_ADDR)
Write only
bit from lsb | description |
---|---|
15-0 | Next SD/DMA DMA transfer size in 2048 bytes step.
ex. 0 = 0x00000000, 1 = 0x00000800, 2 = 0x00001000... This is in ED64 ROM address space, ex. 0xB0000000 on CPU = 0x10000000 on PI = 0x00000000 on ED64 ROM. |
0x08040010 (REG_MSG)
TBA
0x08040014 (REG_DMA_CFG)
Write only
value | description |
---|---|
1 | SD -> Cart |
2 | Cart -> SD |
3 | USB -> Cart |
4 | Cart -> USB |
Note that above table numbers are value, not "bit from lsb".
You must set REG_DMA_LEN and REG_DMA_RAM_ADDR before writing this register.
0x08040018 (REG_SPI)
Read/Write
bit from lsb | description |
---|---|
7-0 | dat/cmd value. Bits are shifted in from lsb if 1bit mode. |
Writing value to this invokes clock CLK on SD card.
You should also write this to read. (write value is ignored)
0x0804001C (REG_SPI_CFG)
Write only
bit from lsb | description |
---|---|
5 | Bits transferred on writing REG_SPI: 0=8bits 1=1bit |
4 | Which line to R/W: 0=CMD 1=DAT |
3 | Read or write (on writing REG_SPI): 0=write 1=read |
2 | Slave Select line on SD card |
1-0 | CLK speed: 10=init 01=25MHz 00=50MHz |
0x08040020 (REG_KEY)
Write only
bit from lsb | description |
---|---|
15-0 | Enable or disable ED64 registers: 0=disable, 0x1234=enable |
Note that you should dummy-read REG_CFG before writing to REG_KEY, or it may be ignored (glitch).
0x08040024 (REG_SAV_CFG)
Write only
bit from lsb | description |
---|---|
15 | always 1? |
7 | unknown but 1? |
3 | SRAM size: 0=32KiB 1=128KiB |
2 | EEPROM size: 0=4kbit 1=16kbit |
1 | SRAM ON: 1=SRAM |
0 | EEPROM ON: 1=EEPROM |
But this register should be treated as a value not bitfields (like REG_DMA_CFG)
value | description |
---|---|
0x8080 | Save is disabled |
0x8082 | 32KiB SRAM enabled |
0x808A | 128KiB SRAM enabled |
0x8081 | 4kbit EEPROM enabled |
0x8085 | 16kbit EEPROM enabled |
0x8088 | 128KiB Flash enabled (!?) |
0x08040028 (REG_SEC)
TBA
0x0804002C (REG_VER)
Read only
bit from lsb | description |
---|---|
15-8 | HW major version |
7-0 | HW minor version |
ex. 0x0304 for HW v3.04
0x08040030 (I2C/RTC)
Read/Write
bit from lsb | description |
---|---|
2 | CLK |
0 | DAT |
You must set DAT=1 before read, or you'll get always DAT=0 (because of I2C's open-drain).
DS1337 (RTC) at address 0x58.
0x08040040 (REG_CFG_CNT)
TBA
0x08040044 (REG_CFG_DAT)
TBA
0x08040048 (REG_MAX_MSG)
Read/Write
bit from lsb | description |
---|---|
14 | ? |
13 | 1=SDHC |
12 | 1=SD card initialized |
11-10 | tvtype (value that IPL3 sets) |
9 | 1=tvtype in REG_MAX_MSG is set |
8 | 1=FPGA configured |
0x0804004C (REG_CRC)
TBA
USB Serial Communication
Common Code
Before communication, you must enable ED64 registers.
TBA
Sending Data to the Host
You should transfer data from RDRAM to some area on cart "ROM" area first, then use Cart->USB DMA on ED64.
TBA
Reading Data from the Host
You should use USB->Cart DMA on ED64 first, then transfer data from cart ROM area to RDRAM.
TBA