COP1
Overview
The COP1 is the FPU of the main CPU. It operates on floats (either 32 bit singles or 64 bit doubles).
Just like the main CPU, the COP1 has 32 registers which are each 64 bit wide. Unlike the main CPU registers, all registers are equal (there is no zero register).
Getting data to/from the COP1
Numbers can be passed from main registers to FPU registers via MTC1 (32 bit) and DMTC1 (64 bit). For the way back, use MFC1/DMFC1. Alternatively, numbers can be loaded from RAM via LWC1/LDC1 and stored via SWC1/SDC1.
Supported formats and conversions
The instructions above simply transfer bits. In order to actually calculate, they need to be interpreted correctly. The COP1 understands four formats:
| Name | Abbreviation | Explanation |
|---|---|---|
| Single | S | 32 bit float |
| Double | D | 64 bit double |
| Word | W | 32 bit integer |
| Long | Long | 64 bit integer |
The COP1 can only perform calculations on singles and doubles; word and long are temporary formats merely used for conversion.
Example: The following snippet puts 6 into V0, which is then moved to the COP1 into F0. It then converts that number to a double and puts it into F2. At the end, F2 will have the value 6.0:
ORI V0, R0, 6
MTC1 V0, F0
CVT.D.W F2, F0 // read: convert to Double from Word
The COP1 supports almost all conversions:
| From Single | From Double | From Word | From Long | |
|---|---|---|---|---|
| To Single | N/A | CVT.S.D | CVT.S.W | CVT.S.L |
| To Double | CVT.D.S | N/A | CVT.D.W | CVT.D.L |
| To Word | CVT.W.S | CVT.W.D | N/A | (doesn't exist) |
| To Long | CVT.L.S | CVT.L.D | (doesn't exist) | N/A |
Rounding modes and inexact results
Most of conversions mentioned above, but also most regular instructions can be lossy. When that happens, the COP1 has to perform some sort of rounding to fit the result in the destination. It provides four modes:
- ROUND: Round towards nearest number (e.g. 4.4 => 4 and 4.6 => 5),
- TRUNC: Round towards zero (e.g. 4.9 => 4 and -4.9 => 4),
- CEIL: Round towards larger number (e.g. 4.1 => 5 and -4.1 => -4),
- FLOOR: Round towards smaller number (e.g. 4.9 => 4 and -4.9 => -5).
The COP1 has a configurable rounding mode in FCSR (see below), which is applied for most instructions where it's applicable. For the specific case of float->int conversions, it provides specialized instructions that overwrite the global rounding mode: ROUND.x.y, TRUNC.x.y, CEIL.x.y, FLOOR.x.y (where x is either W or L and y is either S or D; all 16 combinations are supported).
When rounding happens, inexact is signaled (see exceptions below).
FCSR
In addition to the data registers, the COP1 also provides the Floating Point Status Register, is read via CFC1 and written through CTC1 (using index 31). It provides the following bits:
| Bits | Description |
|---|---|
| 0 to 1 | RoundingMode: Nearest (ROUND) = 0, Zero (TRUNC) = 1, PositiveInfinity (CEIL) = 2, NegativeInfinity (FLOOR) = 3 |
| 2 | Flag: Inexact Operation |
| 3 | Flag: Underflow |
| 4 | Flag: Overflow |
| 5 | Flag: Division By Zero |
| 6 | Flag: Invalid Operation |
| 7 | Enable: Inexact Operation |
| 8 | Enable: Underflow |
| 9 | Enable: Overflow |
| 10 | Enable: Division By Zero |
| 11 | Enable: Invalid Operation |
| 12 | Cause: Inexact Operation |
| 13 | Cause: Underflow |
| 14 | Cause: Overflow |
| 15 | Cause: Division By Zero |
| 16 | Cause: Invalid Operation |
| 17 | Cause: Unimplemented Operation |
| 23 | Condition |
| 24 | Flush Denorm To Zero |
Exceptions Overview
The COP1 supports 6 exceptions:
- Inexact: The destination can't hold the full result, so some data loss occurred and rounding was performed.
- Underflow: The resulting number was so small it was rounded to 0. This is always in combination with inexact. (The COP1 has a quirk here: Unlike other CPUs (e.g. x64 or arm64), the rounding modes FLOOR/CEIL are taken literally even on underflow; if the result is smaller than the smallest possible float, it might not be rounded to 0 but to the minimum regular float).
- Overflow: The resulting number was so large it couldn't be represented as a regular number and was instead "rounded up to infinity" (which is a special floating point value). This is always in combination with inexact.
- Division By Zero: This just happens for DIV.S and DIV.D when the divisor is 0.
- Invalid Operation: This happens in a bunch of special cases (see "Special Cases" below).
- Unimplemented Operation: This happens in a bunch of special cases (see "Special Cases" below).
Instructions that can fire exceptions (e.g. ADD.S, CVT.S.W) always clear all Cause bits that aren't being signaled in this specific instructions. For example, CVT.W.S from 5.5 to an int would affect the bits in the following way:
- Clear all Cause bits
- Perform operation
- Set "Cause: Inexact"
- If "Enable: Inexact" is true, fire exception. Otherwise, set "Flag: Inexact"
This means that Cause be looked at to see the result of the directly preceding instruction. Flags however are cumulative: They are true if any instruction since the last clear signaled that exception, assuming the exception was disabled.
Unimplemented Operation is special as it can't be disabled - if it happens, it will always fire.
Floating Point Numbers
At this point, it makes sense to take a quick look at what floats actually are. The following is the bit representation of a single (doubles work exactly the same, but have more bits in the exponent and the mantissa):
| 31 | 30 - 23 | 22 - 0 |
|---|---|---|
| Sign (1 bit) | Exponent (8 bits) | Mantissa (23 bits) |
If the sign bit is 0, the number is positive. If it is 1, the number is negative (because of this, a floating point number is easily negated - just XOR with 0x80000000).
There are some special cases for the exponent and mantissa:
| Sign bit | Exponent | Mantissa | Description |
|---|---|---|---|
| 0 | 0 | 0 | Regular zero |
| 1 | 0 | 0 | "Negative zero", which is considered equal to regular zero |
| any | 0 | != 0 | Denormal/subnormal |
| 0 | 0xFF | 0 | Positive Infinity |
| 1 | 0xFF | 0 | Negative Infinity |
| any | 0xFF | != 0 with highest bit 0 | sNAN (signaling Not-A-Number) |
| any | 0xFF | != 0 with highest bit 1 | qNAN (quiet Not-A-Number) |
| 0 | 0<x<0xFF | any | A regular positive number |
| 1 | 0<x<0xFF | any | A regular negative number |
Knowing this, determining special cases and can be done by done simple bit operations:
fn is_zero(f: u32) -> bool { f & 0x7FFF_FFFF == 0 }
fn is_subnormal(f: u32) -> bool { ((f & 0x7F80_0000) == 0) && ((f & 0x7F_FFFF) != 0) }
fn is_nan(f: u32) -> bool { ((f & 0x7F80_0000) == 0x7F80_0000) && ((f & 0x7F_FFFF) != 0) }
fn is_quiet_nan(f: u32) -> bool { (f & 0x7FC0_0000) == 0x7FC0_0000) }
fn absolute_value(f: u32) -> bool { f & 0x7FFF_FFFF }
fn negate(f: u32) -> bool { f ^ 0x8000_0000 }