Audio Interface
The Audio Interface (or AI) is one of multiple I/O interfaces in the RCP, which is used to playback audio samples. It is a very simple audio processor: it fetches samples via DMA from RDRAM at a specified rate, and then outputs them. It performs absolutely no conversion on the samples: any audio processing functionality (decompression, mixing, etc.) must be performed by either the CPU or the RSP.
Memory mapped registers are used to configure the AI and initiate DMA transfers. The base address for these registers is 0x0450 0000, also known as AI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add 0xA000 0000 to the address. As an example, to directly write to the AI_LENGTH register, use address 0xA450 0004.
Overview
AI allows to playback samples via a DMA channel. The CPU prepares a buffer of samples in RDRAM, then writes the AI registers to setup a DMA transfer specifying the buffer address and the length. The AI starts playing back those samples in background. Like the RSP and the RDP DMAs, also the AI DMAs has a double-buffering mechanism, so it is possible to enqueue a second buffer while the first one is playing back. This allows for continuous playback: as soon as a buffer is finished, a second is hopefully ready for playback so that the audio is uninterrupted.
AI only supports 16-bit, stereo samples. The playback rate (frequency) is instead configurable.
Connected to the DMA channel, there is a IRQ triggered via MI. Contrary to the usual working of DMAs, the AI IRQ is triggered when a DMA transfer starts, not when it ends. This can be intuitively explained: the AI wants to notify the CPU to prepare and enqueue a new buffer while a buffer is currently playing, so that the hopefully the new one will be ready by the time the current one finishes, to allow uninterrupted playback. If the AI generated the interrupt at the end of the buffer, that would be too late to enqueue a new one without audio crackings, which in turns means that the CPU wouldn't be able to rely on the IRQ for audio pacing.
Registers
Table Notation:
R = Readable bit W = Writable bit U = Undefined/Unused bit -n = Default value n at power on [x:y] = Specifies bits x to y, inclusively
AI_DRAM_ADDR 0x0450 0000
| ||||||||
|---|---|---|---|---|---|---|---|---|
| 31:24 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
| — | — | — | — | — | — | — | — | |
| 23:16 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
| DRAM_ADDR[23:16] | ||||||||
| 15:8 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
| DRAM_ADDR[15:8] | ||||||||
| 7:0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 | W-0 |
| DRAM_ADDR[7:0] | ||||||||
| bit 23-0 | DRAM_ADDR[23:0]: RDRAM address used for next DMA transfer |
Extra Details:
- Read access
- The register is write-only. Reading it returns a mirror of AI_LENGTH.