Video Interface: Difference between revisions
Some usage info for VI test registers
(Document that H_SYNC drives RDRAM refresh timings) |
(Some usage info for VI test registers) |
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| 16 | DEDITHER_FILTER_ENABLE | Dedither Enable bit <br>1 {{=}} Dedither filter is enabled (normally used for 16-bit framebuffers; this may cause vertical banding if anti-aliasing is disabled [https://github.com/DragonMinded/libdragon/issues/159 as seen here]) <br>0 {{=}} Dedither filter is disabled (normally used for 32-bit color)
| 15-12 | PIXEL_ADVANCE[3:0] | Use <code>0b0011</code> for most effective behavior
| 11 | KILL_WE | Diagnostics only, possibly kills VI DMA writes to line buffers making them safe to access via the test registers.
| 10 | Undefined | Initialized to <code>0</code>
| 9-8 | AA_MODE[1:0] | Anti-Alias Mode <br>11 {{=}} AA and resampling disabled, replicate pixels without interpolation <br>10 {{=}} AA disabled, resampling enabled, and operate as if everything is covered <br>01 {{=}} AA enabled, resampling enabled, and only fetches extra lines as needed <br>00 {{=}} AA enabled, resampling enabled, and will always fetch extra lines
| 7 | TEST_MODE | Diagnostics only, enables usage of the line buffer test registers VI_BUFTEST_ADDR/VI_BUFTEST_DATA. KILL_WE should also be set to avoid access races between the VI and CPU.
| 6 | SERRATE | Required if interlacing, permitted when progressive, often disabled <br>1 {{=}} Enabled <br>0 {{=}} Disabled
| 5 | VBUS_CLOCK_ENABLE | Vbus Clock Enable <br>1 {{=}} Enabled <br>0 {{=}} Disabled <br>{{spaces|4}}'''''Warning: Always leave disabled!''' Setting this bit enables a second driver, which will output on the same pin as another driver, possibly causing physical console damage.''
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{{#invoke:Register table|definitions
| 31-7 | Undefined | Initialized to <code>0</code>
| 6-0 | TEST_ADDR[6:0] |
}}
==== <span style="display:none;">0x0440 003C - VI_STAGED_DATA ====
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{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-0 | STAGED_DATA[31:0] | Reads from this register returns 32 bits of line buffer data at the address specified in VI_TEST_ADDR. Writes to this register emplace 32 bits of data into the line buffer at the address specified in VI_TEST_ADDR. Usage requires TEST_MODE to be set in VI_CTRL.
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