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Video Interface (view source)

Revision as of 03:24, 23 March 2023

No change in size ,  1 year ago
convention we want to use for bitranges is apparently [number:number] not <number:number>
VisualWikitext
m (→‎0x0440 0020 - VI_H_SYNC_LEAP: these registers are 12 bits wide, not 10)
(convention we want to use for bitranges is apparently [number:number] not <number:number>)
Line 123:
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || RW-0 || RW-0
|-
| colspan="4" | PIXEL_ADVANCE<[3:0>] || KILL_WE || — || colspan="2" | AA_MODE<[1:0>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| TEST_MODE || SERRATE || style="font-size: 70%;" | VBUS_CLOCK_ENABLE || DIVOT_ENABLE || GAMMA_ENABLE || style="font-size: 70%;" | GAMMA_DITHER_ENABLE || colspan="2" | TYPE<[1:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-17 | Undefined | Initialized to <code>0</code>
| 16 | DEDITHER_FILTER_ENABLE | Dedither Enable bit <br>1 {{=}} Dedither filter is enabled (normally used for 16-bit framebuffers; this may cause vertical banding if anti-aliasing is disabled [https://github.com/DragonMinded/libdragon/issues/159 as seen here]) <br>0 {{=}} Dedither filter is disabled (normally used for 32-bit color)
| 15-12 | PIXEL_ADVANCE<[3:0>] | Use <code>0b0011</code> for most effective behavior
| 11 | KILL_WE | Diagnostics only
| 10 | Undefined | Initialized to <code>0</code>
| 9-8 | AA_MODE<[1:0>] | Anti-Alias Mode <br>11 {{=}} AA and resampling disabled, replicate pixels without interpolation <br>10 {{=}} AA disabled, resampling enabled, and operate as if everything is covered <br>01 {{=}} AA enabled, resampling enabled, and only fetches extra lines as needed <br>00 {{=}} AA enabled, resampling enabled, and will always fetch extra lines
| 7 | TEST_MODE | Diagnostics only
| 6 | SERRATE | Normally enabled if interlacing, otherwise disabled <br>1 {{=}} Enabled <br>0 {{=}} Disabled
Line 142:
| 3 | GAMMA_ENABLE | Fixes non-linear gamma in TV screens (more details below) <br>1 {{=}} Enabled <br>0 {{=}} Disabled
| 2 | GAMMA_DITHER_ENABLE | Adds randomized noise to the video output, in the least significant bits to remove mach banding artifacts <br>1 {{=}} Enabled (usually set unless banding artifacts are desired for extra effect) <br>0 {{=}} Disabled
| 1-0 | TYPE<[1:0>] | Video pixel size, also known as color bit depth <br>11 {{=}} 8/8/8/8 (32 bit color) <br>10 {{=}} 5/5/5/3 (16 bit color, technically 18 bits wide) <br>01 {{=}} reserved <br>00 {{=}} blank (no data and no sync, TV screens will either show static or nothing)
}}
'''Extra Details:'''
Line 162:
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | ORIGIN<[23:16>]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | ORIGIN<[15:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | ORIGIN<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-24 | Undefined | Initialized to <code>0</code>
| 23-0 | ORIGIN<[23:0>] | RDRAM base address of the video output Frame Buffer. This can be changed as needed to implement double or triple buffering.
}}
==== <span style="display:none;">0x0440 0008 - VI_WIDTH ====
Line 190:
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | WIDTH<[11:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | WIDTH<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-12 | Undefined | Initialized to <code>0</code>
| 11-0 | WIDTH<[11:0>] | This is the width in pixels of the frame buffer if you draw to the frame buffer based on a different width than what is given here the image will drift with each line to the left or right. The common values are 320 and 640, the maximum value is 4095. The same value would also be used on drawing commands for clipping or scissors. This can also be used with High Res interlacing modes to change the odd and even lines of the frame buffer to be drawn to screen by doubling the width of this value and changing the VI_ORIGIN register to the odd or even field being displayed.
}}
==== <span style="display:none;">0x0440 000C - VI_V_INTR ====
Line 214:
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-1 || RW-1
|-
| — || — || — || — || — || — || colspan="2" | V_INTR<[9:8>]
{{#invoke:Register table|row|7:0}}
| RW-1 || RW-1 || RW-1 || RW-1 || RW-1 || RW-1 || RW-1 || RW-1
|-
| colspan="8" | V_INTR<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-10 | Undefined | Initialized to <code>0</code>
| 9-0 | V_INTR<[9:0>] | When VI_V_CURRENT reaches this half-line number, a VI Interrupt is triggered. Usually set to the last line containing pixel data.<br>Default value of <code>0x3FF</code>
}}
==== <span style="display:none;">0x0440 0010 - VI_V_CURRENT ====
Line 238:
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || style="font-size: 88%;" colspan="2" | V_CURRENT<[9:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | V_CURRENT<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-10 | Undefined | Initialized to <code>0</code>
| 9-0 | V_CURRENT<[9:0>] | The current half line, sampled once per line. Bit 0 is constant for non-interlaced modes. In interlaced modes, bit 0 gives the field number. Writing anything to this register clears the currently triggered VI Interrupt.
}}
==== <span style="display:none;">0x0440 0014 - VI_BURST ====
Line 254:
| U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || colspan="6" | BURST_START<[9:4>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="4" | BURST_START<[3:0>] || colspan="4" | VSYNC_WIDTH<[3:0>]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | BURST_WIDTH<[7:0>]
{{#invoke:Register table|row|7:0}}
| RW-1 || RW-1 || RW-0 || RW-1 || RW-0 || RW-0 || RW-0 || RW-1
|-
| colspan="8" | HSYNC_WIDTH<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-30 | Undefined | Initialized to <code>0</code>
| 29-20 | BURST_START<[9:0>] | Start of color burst in pixels from hsync
| 19-16 | VSYNC_WIDTH<[3:0>] | Vertical sync width in half lines
| 15-8 | BURST_WIDTH<[7:0>] | Color burst width in pixels
| 7-0 | HSYNC_WIDTH<[7:0>] | Horizontal sync width in pixels<br>Default value of <code>0x01</code>
}}
'''Examples:'''
Line 300:
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | V_SYNC<[9:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | V_SYNC<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-10 | Undefined | Initialized to <code>0</code>
| 9-0 | V_SYNC<[9:0>] | Total visible and non-visible lines. This should match either NTSC (non-interlaced: <code>0x20D</code>, interlaced: <code>0x20C</code>) or PAL (non-interlaced: <code>0x271</code>, interlaced: <code>0x270</code>)
}}
==== <span style="display:none;">0x0440 001C - VI_H_SYNC ====
Line 320:
| U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || colspan="5" | LEAP<[4:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || RW-1 || RW-1 || RW-1 || RW-1
|-
| — || — || — || — || colspan="4" | H_SYNC<[11:8>]
{{#invoke:Register table|row|7:0}}
| RW-1 || RW-1 || RW-1 || RW-1 || RW-1 || RW-1 || RW-1 || RW-1
|-
| colspan="8" | H_SYNC<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-21 | Undefined | Initialized to <code>0</code>
| 20-16 | LEAP<[4:0>] | 5-bit leap pattern used only for PAL. Should always use standard value of <code>0x15</code>
| 15-12 | Undefined | Initialized to <code>0</code>
| 11-0 | H_SYNC<[11:0>] | Total width of a line, in 1/4 pixel units. Should always use standard values: NTSC (<code>0xC15</code>) or PAL (<code>0xC69</code>)<br>Default value of <code>0x7FF</code>
}}
==== <span style="display:none;">0x0440 0020 - VI_H_SYNC_LEAP ====
Line 342:
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | LEAP_A<[11:8>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | LEAP_A<[7:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | LEAP_B<[11:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | LEAP_B<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-28 | Undefined | Initialized to <code>0</code>
| 27-16 | LEAP_A<[11:0>] | NTSC: Identical to H_SYNC width. PAL: <code>0xC6E</code>
| 15-12 | Undefined | Initialized to <code>0</code>
| 11-0 | LEAP_B<[11:0>] | NTSC: Identical to H_SYNC width. PAL: <code>0xC6F</code>
}}
 
Line 369:
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | H_START<[9:8>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | H_START<[7:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | H_END<[9:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | H_END<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-26 | Undefined | Initialized to <code>0</code>
| 25-16 | H_START<[9:0>] | Start of the active video image, in screen pixels. Typical values: NTSC (<code>0x06C</code>) or PAL (<code>0x080</code>)
| 15-10 | Undefined | Initialized to <code>0</code>
| 9-0 | H_END<[9:0>] | End of the active video image, in screen pixels from hsync. Typical values: NTSC (<code>0x2EC</code>) or PAL (<code>0x300</code>)
}}
==== <span style="display:none;">0x0440 0028 - VI_V_VIDEO ====
Line 395:
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | V_START<[9:8>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | V_START<[7:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || colspan="2" | V_END<[9:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | V_END<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-26 | Undefined | Initialized to <code>0</code>
| 25-16 | V_START<[9:0>] | Start of the active video image, in screen half-lines. Typical values: NTSC (<code>0x025</code>) or PAL (<code>0x05F</code>)
| 15-10 | Undefined | Initialized to <code>0</code>
| 9-0 | V_END<[9:0>] | End of the active video image, in screen half-lines from vsync. Typical values: NTSC (<code>0x1FF</code>) or PAL (<code>0x239</code>)
}}
==== <span style="display:none;">0x0440 002C - VI_V_BURST ====
Line 421:
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || style="font-size: 90%;" colspan="2" | V_BURST_START<[9:8>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | V_BURST_START<[7:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0
|-
| — || — || — || — || — || — || style="font-size: 90%;" colspan="2" | V_BURST_END<[9:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | V_BURST_END<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-26 | Undefined | Initialized to <code>0</code>
| 25-16 | V_BURST_START<[9:0>] | Start of the color burst enable, in half-lines. Typical values: NTSC (<code>0x00E</code>) or PAL (<code>0x009</code>)
| 15-10 | Undefined | Initialized to <code>0</code>
| 9-0 | V_BURST_END<[9:0>] | End of the color burst enable, in half-lines. Typical values: NTSC (<code>0x204</code>) or PAL (<code>0x26B</code>)
}}
==== <span style="display:none;">0x0440 0030 - VI_X_SCALE ====
Line 447:
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | X_OFFSET<[11:8>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | X_OFFSET<[7:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | X_SCALE<[11:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | X_SCALE<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-28 | Undefined | Initialized to <code>0</code>
| 27-16 | X_OFFSET<[11:0>] | Horizontal subpixel offset (2.10 format)
| 15-12 | Undefined | Initialized to <code>0</code>
| 11-0 | X_SCALE<[11:0>] | 1/horizontal scale up factor (2.10 format)
}}
==== <span style="display:none;">0x0440 0034 - VI_Y_SCALE ====
Line 473:
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | Y_OFFSET<[11:8>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | Y_OFFSET<[7:0>]
{{#invoke:Register table|row|15:8}}
| U-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || — || — || — || colspan="4" | Y_SCALE<[11:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | Y_SCALE<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-28 | Undefined | Initialized to <code>0</code>
| 27-16 | Y_OFFSET<[11:0>] | Vertical subpixel offset (2.10 format)
| 15-12 | Undefined | Initialized to <code>0</code>
| 11-0 | Y_SCALE<[11:0>] | 1/vertical scale up factor (2.10 format)
}}
==== <span style="display:none;">0x0440 0038 - VI_TEST_ADDR ====
Line 511:
| U-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| — || colspan="7" | TEST_ADDR<[6:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-7 | Undefined | Initialized to <code>0</code>
| 6-0 | TEST_ADDR<[6:0>] | Diagnostics only, usage unknown
}}
==== <span style="display:none;">0x0440 003C - VI_STAGED_DATA ====
Line 523:
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | STAGED_DATA<[31:24>]
{{#invoke:Register table|row|23:16}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | STAGED_DATA<[23:16>]
{{#invoke:Register table|row|15:8}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | STAGED_DATA<[15:8>]
{{#invoke:Register table|row|7:0}}
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="8" | STAGED_DATA<[7:0>]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-0 | STAGED_DATA<[31:0>] | Diagnostics only, usage unknown
}}
= How to use this information =
Lidnariq
60

edits

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