Video Interface: Difference between revisions

Reorganized two registers using experimental formatting; may be changed or reverted in future edits.
(Added details on the High Res images on interlacing)
(Reorganized two registers using experimental formatting; may be changed or reverted in future edits.)
Line 109:
When using the VI Interface this should be all you need. For other Interfaces there are some situations that it should be accessed with a different technique, so they will be covered in more depth where it's relevant.
 
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==== 0x0440 0000 - VI_CONTROL_REG ====
==== <span style="display:none;">0x0440 0000 - VI_CTRL</span> ====
{| class="wikitable" style="text-align: center; table-layout: fixed; width: 1200px;"
! colspan="9" | VI_CTRL <code>0x0440 0000</code>
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
! rowspan="2" style="font-size: 115%;" | 31:24
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| — || — || — || — || — || — || — || —
 
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
! rowspan="2" style="font-size: 115%;" | 31:24
| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || RW-0
|-
| — || — || — || — || — || — || — || style="font-size: 70%;" | DITHER_FILTER_ENABLE
 
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
! rowspan="2" style="font-size: 115%;" | 15:8
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || RW-0 || RW-0
|-
| colspan="4" | PIXEL_ADVANCE<3:0> || KILL_WE || — || colspan="2" | AA_MODE<1:0>
 
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
! rowspan="2" style="font-size: 115%;" | 7:0
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| TEST_MODE || SERRATE || style="font-size: 70%;" | VBUS_CLOCK_ENABLE || DIVOT_ENABLE || GAMMA_ENABLE || style="font-size: 70%;" | GAMMA_DITHER_ENABLE || colspan="2" | TYPE<1:0>
|}
{| style="font-size: 85%; line-height: 1.6em;"
| style="padding-right: 9px; vertical-align:top;" | bit 31-17 || '''Unimplemented:''' Read as <code>0</code>
|-
| style="padding-right: 9px; vertical-align:top;" | bit 16 || '''DITHER_FILTER_ENABLE:''' Dither Enable bit <br>1 = Dither filter is enabled (normally used for 16-bit color) <br>0 = Dither filter is disabled (normally used for 32-bit color) <br>{{spaces|4}}Using the filter disables the dithering effects. It's generally assumed that if enabled, dithering would occur in the RDP instead.
|-
| style="padding-right: 9px; vertical-align:top;" | bit 15-12 || '''PIXEL_ADVANCE<3:0>:''' Use <code>0b0011</code> for most effective behavior
|-
| style="padding-right: 9px; vertical-align:top;" | bit 11 || '''KILL_WE:''' Diagnostics only
|-
| style="padding-right: 9px; vertical-align:top;" | bit 10 || '''Unimplemented:''' Read as <code>0</code>
|-
| style="padding-right: 9px; vertical-align:top;" | bit 9-8 || '''AA_MODE<1:0>:''' Anti-Alias Mode
11 = AA and resampling disabled, replicate pixels without interpolation
<br>10 = AA disabled, resampling enabled, and operate as if everything is covered
<br>01 = AA enabled, resampling enabled, and only fetches extra lines as needed
<br>00 = AA enabled, resampling enabled, and will always fetch extra lines
|-
| style="padding-right: 9px; vertical-align:top;" | bit 7 || '''TEST_MODE:''' Diagnostics only
|-
| style="padding-right: 9px; vertical-align:top;" | bit 6 || '''SERRATE:''' Normally enabled if interlacing, otherwise disabled <br>1 = Enabled <br>0 = Disabled
|-
| style="padding-right: 9px; vertical-align:top;" | bit 5 || '''VBUS_CLOCK_ENABLE:''' Vbus Clock Enable <br>1 = Vbus clock enabled <br>0 = Vbus clock disabled <br>{{spaces|4}}'''''Warning: Always leave disabled!''' Setting this bit enables a second driver, which when enabled will output on the same pin as another driver, possibly causing physical console damage.''
|-
| style="padding-right: 9px; vertical-align:top;" | bit 4 || '''DIVOT_ENABLE:''' Fixes minor artifacts left over from anti-aliasing (more details below) <br>1 = Enabled (usually used if AA is enabled) <br>0 = Disabled
|-
| style="padding-right: 9px; vertical-align:top;" | bit 3 || '''GAMMA_ENABLE:''' Fixes non-linear gamma in TV screens (more details below) <br>1 = Enabled <br>0 = Disabled
|-
| style="padding-right: 9px; vertical-align:top;" | bit 2 || '''GAMMA_DITHER_ENABLE:''' Adds randomized noise to the video output, in the least significant bits to remove mach banding artifacts
1 = Enabled (usually set unless banding artifacts are desired for extra effect)
<br>0 = Disabled
|-
| style="padding-right: 9px; vertical-align:top;" | bit 1-0 || '''TYPE<1:0>:''' Video pixel size, also known as color bit depth
11 = 8/8/8/8 (32 bit color)
<br>10 = 5/5/5/3 (16 bit color, technically 18 bits wide)
<br>01 = reserved
<br>00 = blank (no data and no sync, TV screens will either show static or nothing)
|}
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==== 0x0440 0004 - VI_DRAM_ADDR_REG - R/(W default) ====
This is the address of the FrameBuffer that should be sent to the TV, it's nice that the buffer doesn't have to be copied and can be sent directly to the TV. If you are using double or triple buffered screens this is the value that you will be changing to display the next screen.
Line 125 ⟶ 189:
If interrupts are used, writing to this reg will reset the interrupt line in the RCP for the the next frame (this mostly affects the address 32x04300008 and bit 3 for the VI interrupt)
 
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==== 0x0440 0014 - VI_BURST_REG - R/(W default) ====
==== <span style="display:none;">0x0440 0014 - VI_BURST</span> ====
This register holds 4 related values:
{| class="wikitable" style="text-align: center; table-layout: fixed; min-width: 500px;"
 
! colspan="9" | VI_BURST <code>0x0440 0014</code>
* [7:0] horizontal sync width in pixels
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
* [15:8] color burst width in pixels
! rowspan="2" style="font-size: 115%;" | 31:24
* [19:16] vertical sync width in half lines
| U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
* [29:20] start of color burst in pixels from h-sync
|-
 
| — || — || colspan="6" | BURST_START<9:4>
An example value for NTSC @ any resolution is 0x03e52239 or 00 00'0011'1110 0101 0010'0010 0011'1001 in binary.
 
* horizontal sync width in pixels: 57 (decimal)
* color burst width in pixels: 34 (decimal)
* vertical sync width in half lines: 5 (decimal)
* start of color burst in pixels from h-sync: 62 (decimal)
 
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
An example value for PAL @ any resolution is 0x0404233a or 00 00'0100'0000 0100 0010'0011 0011'1010 in binary
! rowspan="2" style="font-size: 115%;" | 23:16
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
|-
| colspan="4" | BURST_START<3:0> || colspan="4" | VSYNC_WIDTH<3:0>
 
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
* horizontal sync width in pixels: 58 (decimal)
! rowspan="2" style="font-size: 115%;" | 15:8
* color burst width in pixels: 35 (decimal)
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0
* vertical sync width in half lines: 4 (decimal)
|-
* start of color burst in pixels from h-sync: 64 (decimal)
| colspan="8" | BURST_WIDTH<7:0>
 
|- style="font-size: 85%; line-height: 0.9em; background-color: #caccd0;"
! rowspan="2" style="font-size: 115%;" | 7:0
| RW-1 || RW-1 || RW-0 || RW-1 || RW-0 || RW-0 || RW-0 || RW-1
|-
| colspan="8" | HSYNC_WIDTH<7:0>
|}
{| style="font-size: 85%; line-height: 1.6em;"
| style="padding-right: 9px; vertical-align:top;" | bit 31-30 || '''Unimplemented:''' Read as <code>0</code>
|-
| style="padding-right: 9px; vertical-align:top;" | bit 29-20 || '''BURST_START<9:0>:''' Start of color burst in pixels from hsync
|-
| style="padding-right: 9px; vertical-align:top;" | bit 19-16 || '''VSYNC_WIDTH<3:0>:''' Vertical sync width in half lines
|-
| style="padding-right: 9px; vertical-align:top;" | bit 15-8 || '''BURST_WIDTH<7:0>:''' Color burst width in pixels
|-
| style="padding-right: 9px; vertical-align:top;" | bit 7-0 || '''HSYNC_WIDTH<7:0>:''' Horizontal sync width in pixels<br>Default value of <code>0xD1</code>
|}
'''Examples:'''
: NTSC @ any resolution is <code>0x03E52239</code>
:* horizontal sync width in pixels: 57 (decimal)
:* color burst width in pixels: 34 (decimal)
:* vertical sync width in half lines: 5 (decimal)
:* start of color burst in pixels from h-sync: 62 (decimal)
: PAL @ any resolution is <code>0x0404233A</code>
:* horizontal sync width in pixels: 58 (decimal)
:* color burst width in pixels: 35 (decimal)
:* vertical sync width in half lines: 4 (decimal)
:* start of color burst in pixels from h-sync: 64 (decimal)
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==== 0x0440 0018 - VI_V_SYNC_REG - R/(W default) ====
'''Always set to the Appropriate value for the Standard being used'''