Video Interface: Difference between revisions
Added the clocks and how they are set in the N64 as well as added some details on how some of the reg's work in the VI core
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Mazamars312 (talk | contribs) (Added the clocks and how they are set in the N64 as well as added some details on how some of the reg's work in the VI core) |
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=== Introduction ===
The Video Interface Registers provide a lot of flexibility, the exact same chips and registers are used to support NTSC, PAL and M-PAL. Below each register will be explained using sample data to clarify how it should be used. All registers are 32-bits in length and should always be written a full word (32-bits) at a time.
=== Video DAC ===
The Video DAC has a 7 bit multiplexed data bus that is used to generate the video signal from the RCP. This allows the N64 to output a 21 bit color output even thou internally it can do 24 bits. Why this lower bit was not used is not explained in any documentation found at this moment.
[[File:N64videosys.png|thumb|Video DAC Bus and waveform. Image from: http://members.optusnet.com.au/eviltim/n64rgb/n64rgb.html]]
The Video DAC clock runs at 4 times the speed of the internal pixel clock so the multiplexing can happen on the VI bus. This 4 clock process outputs the RGB colors and the VSync, Hsync, Clamp and Csync and is reset using a dsync reset signal. This is driven by a pixel clock provided by the MX8330 (IC U7)
{| class="wikitable"
|+
!
!Cycle 1
!Cycle 2
!Cycle 3
!Cycle 4
|-
|D0
|Red 0
|Green 0
|Blue 0
|!Csync
|-
|D1
|Red 1
|Green 1
|Blue 1
|!Hsync
|-
|D2
|Red 2
|Green 2
|Blue 2
|!Clamp
|-
|D3
|Red 3
|Green 3
|Blue 3
|!Vsync
|-
|D4
|Red 4
|Green 4
|Blue 4
|NA
|-
|D5
|Red 5
|Green 5
|Blue 5
|NA
|-
|D6
|Red 6
|Green 6
|Blue 6
|NA
|-
|DSYNC
|HIGH
|HIGH
|HIGH
|Low
|}
There are 3 different pixel clocks that are used in the N64 for the 3 TV standards: <gallery>
File:MX8330 video maths.png|Mx8330 video clock maths and fselect
</gallery>
{| class="wikitable"
|+
!TV Signal Type
!Pixel Clock
!MX8330 Input clock
!MX8330 FSEL input
!Clock Maths useing datasheet
|-
|NTSC
|48.62Mhz
|14.3Mhz
|HIGH
|((14.3 * 4 )* 17) / 5
|-
|PAL
|48.72Mhz
|17.4Mhz
|LOW
|((17.4 * 4 )* 14) / 5
|-
|MPAL
|To be advised
|To be advised
|To be advised
|
|}
=== Video Standards ===
Line 29 ⟶ 121:
==== 0x0440 0010 - VI_V_CURRENT_LINE_REG - RO (Read Only/Writes ignored) ====
This is the line that the VI is currently sending to the TV.
If interrupts are used, writing to this reg will reset the interrupt line in the RCP for the the next frame (this mostly affects the address 32x04300008 and bit 3 for the VI interrupt)
==== 0x0440 0014 - VI_BURST_REG - R/(W default) ====
Line 65 ⟶ 159:
'''Always set to the Appropriate value for the Standard being used'''
* [11:0] total duration of a line in 1/4 pixel units
* [20:16] a 5-bit leap pattern used for PAL only (h_sync_period)
Line 93 ⟶ 187:
==== 0x0440 0024 - VI_H_START_REG ====
* [9:0] end of active video in screen pixels - This advised the VI core where the Start of the image is in terms of the video signal on the horizontal plane - this uses the pixel clock / 4 to align the signal to the screen
* [25:16] start of active video in screen pixels - This advised the VI core where the Start of the image is in terms of the video signal on the horizontal plane - this uses the pixel clock / 4 to align the signal to the screen
NTSC: 0x006c02ec = 0000'00 00'0110'1100 0000'00 10'1110'1100
Line 108 ⟶ 202:
==== 0x0440 0028 - VI_V_START_REG ====
* [9:0] end of active video in screen half-lines - This advised the VI core where the end of the image is in terms of the video signal on the Vertiall plane - this uses the pixel clock / 4 to align the signal to the screen
* [25:16] start of active video in screen half-lines - This advised the VI core where the start of the image is in terms of the video signal on the Vertiall plane - this uses the pixel clock / 4 to align the signal to the screen
NTSC: 0x002501ff = 0000'00 00'0010'0101 0000'00 01'1111'1111
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