Video Interface: Difference between revisions
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Mazamars312 (talk | contribs) (Added the clocks and how they are set in the N64 as well as added some details on how some of the reg's work in the VI core) |
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=== Introduction === |
=== Introduction === |
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The Video Interface Registers provide a lot of flexibility, the exact same chips and registers are used to support NTSC, PAL and M-PAL. Below each register will be explained using sample data to clarify how it should be used. All registers are 32-bits in length and should always be written a full word (32-bits) at a time. |
The Video Interface Registers provide a lot of flexibility, the exact same chips and registers are used to support NTSC, PAL and M-PAL. Below each register will be explained using sample data to clarify how it should be used. All registers are 32-bits in length and should always be written a full word (32-bits) at a time. |
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=== Video DAC === |
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The Video DAC has a 7 bit multiplexed data bus that is used to generate the video signal from the RCP. This allows the N64 to output a 21 bit color output even thou internally it can do 24 bits. Why this lower bit was not used is not explained in any documentation found at this moment. |
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[[File:N64videosys.png|thumb|Video DAC Bus and waveform. Image from: http://members.optusnet.com.au/eviltim/n64rgb/n64rgb.html]] |
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The Video DAC clock runs at 4 times the speed of the internal pixel clock so the multiplexing can happen on the VI bus. This 4 clock process outputs the RGB colors and the VSync, Hsync, Clamp and Csync and is reset using a dsync reset signal. This is driven by a pixel clock provided by the MX8330 (IC U7) |
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{| class="wikitable" |
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|+ |
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! |
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!Cycle 1 |
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!Cycle 2 |
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!Cycle 3 |
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!Cycle 4 |
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|- |
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|D0 |
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|Red 0 |
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|Green 0 |
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|Blue 0 |
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|!Csync |
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|- |
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|D1 |
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|Red 1 |
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|Green 1 |
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|Blue 1 |
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|!Hsync |
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|- |
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|D2 |
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|Red 2 |
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|Green 2 |
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|Blue 2 |
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|!Clamp |
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|- |
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|D3 |
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|Red 3 |
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|Green 3 |
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|Blue 3 |
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|!Vsync |
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|- |
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|D4 |
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|Red 4 |
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|Green 4 |
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|Blue 4 |
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|NA |
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|- |
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|D5 |
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|Red 5 |
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|Green 5 |
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|Blue 5 |
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|NA |
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|- |
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|D6 |
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|Red 6 |
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|Green 6 |
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|Blue 6 |
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|NA |
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|- |
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|DSYNC |
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|HIGH |
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|HIGH |
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|HIGH |
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|Low |
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|} |
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There are 3 different pixel clocks that are used in the N64 for the 3 TV standards: <gallery> |
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File:MX8330 video maths.png|Mx8330 video clock maths and fselect |
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</gallery> |
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{| class="wikitable" |
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|+ |
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!TV Signal Type |
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!Pixel Clock |
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!MX8330 Input clock |
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!MX8330 FSEL input |
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!Clock Maths useing datasheet |
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|- |
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|NTSC |
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|48.62Mhz |
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|14.3Mhz |
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|HIGH |
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|((14.3 * 4 )* 17) / 5 |
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|- |
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|PAL |
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|48.72Mhz |
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|17.4Mhz |
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|LOW |
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|((17.4 * 4 )* 14) / 5 |
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|- |
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|MPAL |
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|To be advised |
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|To be advised |
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|To be advised |
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| |
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|} |
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=== Video Standards === |
=== Video Standards === |
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==== 0x0440 0010 - VI_V_CURRENT_LINE_REG - RO (Read Only/Writes ignored) ==== |
==== 0x0440 0010 - VI_V_CURRENT_LINE_REG - RO (Read Only/Writes ignored) ==== |
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This is the line that the VI is currently sending to the TV |
This is the line that the VI is currently sending to the TV. |
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If interrupts are used, writing to this reg will reset the interrupt line in the RCP for the the next frame (this mostly affects the address 32x04300008 and bit 3 for the VI interrupt) |
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==== 0x0440 0014 - VI_BURST_REG - R/(W default) ==== |
==== 0x0440 0014 - VI_BURST_REG - R/(W default) ==== |
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'''Always set to the Appropriate value for the Standard being used''' |
'''Always set to the Appropriate value for the Standard being used''' |
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* [11:0] total duration of a line in 1/4 pixel units |
* [11:0] total duration of a line in 1/4 pixel units |
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* [20:16] a 5-bit leap pattern used for PAL only (h_sync_period) |
* [20:16] a 5-bit leap pattern used for PAL only (h_sync_period) |
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==== 0x0440 0024 - VI_H_START_REG ==== |
==== 0x0440 0024 - VI_H_START_REG ==== |
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* [9:0] end of active video in screen pixels - This advised the VI core where the Start of the image is in terms of the video signal on the horizontal plane - this uses the pixel clock / 4 to align the signal to the screen |
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* [9:0] end of active video in screen pixels |
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* [25:16] start of active video in screen pixels |
* [25:16] start of active video in screen pixels - This advised the VI core where the Start of the image is in terms of the video signal on the horizontal plane - this uses the pixel clock / 4 to align the signal to the screen |
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NTSC: 0x006c02ec = 0000'00 00'0110'1100 0000'00 10'1110'1100 |
NTSC: 0x006c02ec = 0000'00 00'0110'1100 0000'00 10'1110'1100 |
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==== 0x0440 0028 - VI_V_START_REG ==== |
==== 0x0440 0028 - VI_V_START_REG ==== |
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* [9:0] end of active video in screen half-lines |
* [9:0] end of active video in screen half-lines - This advised the VI core where the end of the image is in terms of the video signal on the Vertiall plane - this uses the pixel clock / 4 to align the signal to the screen |
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* [25:16] start of active video in screen half-lines |
* [25:16] start of active video in screen half-lines - This advised the VI core where the start of the image is in terms of the video signal on the Vertiall plane - this uses the pixel clock / 4 to align the signal to the screen |
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NTSC: 0x002501ff = 0000'00 00'0010'0101 0000'00 01'1111'1111 |
NTSC: 0x002501ff = 0000'00 00'0010'0101 0000'00 01'1111'1111 |