SysAD Interface: Difference between revisions

The address for I-cache reads will always be 256 bit aligned for the address (So that last 5 bits of the address will always be 00000) This is because the I-Cache memory is setup as a 256 aligned entry and there is no smarts in the 4300i CPU to know if all of the cache entry is full. Thus, the CPU must have a full entry in the icache before it can load instructions. The 256 reads run the same as the D-cache reads (and are sequential order). But the command sent to the RCP is the read – 256 it command. And 8x 32 bit data accesses are sent over the SYSAD bus

[[File:Read icache 256bit.png|thumb|796x796px|Read from the CPU that is 256 Bits for the I-cache]]