Serial Interface: Difference between revisions
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In addition to these registers, SI is also in charge of handling the memory mapping of PIF-ROM and PIF-RAM to VR4300. These memories are mapped at physical address <code>0x1FC0 0000</code> (and normally accessed via the uncached segment at <code>0xBFC0 0000</code>).
== Communication protocol with PIF-NUS ==
The communication protocol with PIF-NUS is the low-level data encapsulation performed by the SI to communicate with PIF-NUS. There are 4 supported packets:
* '''RD4B'''. The SI sends on the bus the bits <code>11</code> to identify the packet, followed by bits 10..2 of the address to read. The PIF replies with an ACK followed
== Mapped PIF-ROM and PIF-RAM ==
When the VR4300 access the physical area at <code>0x1FC0 0000</code> - <code>0x1FC0 0FFF</code>, RCP handles the request via SI; the memory access performed via standard MIPS opcode like LW or SW is converted into a I/O communication with PIF, using the serial bus.
There are 4 kind of accesses that are possible
Reading from the PIF_ROM area (<code>0x1FC0 0000</code> - <code>0x1FC0 0FC0</code>) will simply return 0 after boot is finished, because the PIF locks PIF_ROM accesses for security reasons. This is not something that SI is aware of: it will still request the data via the serial bus to PIF, and PIF will simply return 0.
Write accesses to the mapped area are meant to be done as 32-bit words. 16-bit and 8-bit writes behave in a non-standard way, as they affect the whole 32-bit word they are written to: higher bits are sign-extended, while lower bits are reset to 0. For instance, writing the 8-bit value <code>0xAB</code> at offset 2 in PIF_RAM has the same effect as writing the 32-bit word <code>0xFFFFAB00</code> to offset 0 in PIF_RAM. This is the same behavior of write accesses to [[Reality Signal Processor/Interface#DMEM and IMEM|IMEM/DMEM in RSP]]. 64-bit writes only actually write the higher 32-bit word into the written location, so the second half of the write is basically ignored.
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