Serial Interface: Difference between revisions
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Memory mapped registers are used to configure the Serial Interface and initiate DMA reads and writes. The base address for these registers is <code>0x0480 0000</code>, also known as SI_BASE. However, because all memory accesses in the CPU are made using virtual addresses, the following addresses must be offset appropriately. For non-cached reads/writes, add <code>0xA000 0000</code> to the address. As an example, to directly write to the SI_DRAM_ADDR register, use address <code>0xA480 0000</code>.
In addition to these registers, SI is also in charge of handling the memory mapping of PIF-ROM and PIF-RAM to VR4300. These memories are mapped at physical address <code>0x1FC0 0000</code> (and normally accessed via the uncached segment at <code>0xBFC0 0000</code>).
= Registers =▼
== Mapped PIF-ROM and PIF-RAM ==
When the VR4300 access the physical area at <code>0x1FC0 0000</code> - <code>0x1FC0 0FFF</code>, RCP handles the request via SI; the memory access performed via standard MIPS opcode like LW or SW is converted into a I/O communication with PIF, using the serial bus.
Read accesses to the mapped area works as 32-bit, 16-bit or 8-bit loads. 64-bit loads freeze the VR4300 instead, so they must be avoided. All read accesses are blocking: the VR4300 will be locked until the data is read via serial from PIF. In general, it is preferable to use DMA instead so that the transfer can happen in background.
Reading from the PIF_ROM area (<code>0x1FC0 0000</code> - <code>0x1FC0 0FC0</code>) will simply return 0 after boot is finished, because the PIF locks PIF_ROM accesses for security reasons. This is not something that SI is aware of: it will still request the data via the serial bus to PIF, and PIF will simply return 0.
Write accesses to the mapped area are meant to be done as 32-bit words. 16-bit and 8-bit writes behave in a non-standard way, as they affect the whole 32-bit word they are written to: higher bits are sign-extended, while lower bits are reset to 0. For instance, writing the 8-bit value <code>0xAB</code> at offset 2 in PIF_RAM has the same effect as writing the 32-bit word <code>0xFFFFAB00</code> to offset 0 in PIF_RAM. This is the same behavior of write accesses to [[Reality Signal Processor/Interface#DMEM and IMEM|IMEM/DMEM in RSP]]. 64-bit writes only actually write the higher 32-bit word into the written location, so the second half of the write is basically ignored.
Write accesses are non-blocking: the value to be written is cached by the SI interface, and the VR4300 is released. The actual write is performed in background. During the write, the "I/O busy" bit in the <code>SI_STATUS</code> register is set 1. While the bit is set, no further writes, reads or DMAs should be performed as that might cause bus conflicts and thus unwanted results.
Writing to the PIF_ROM area works at the SI level, but the write is then discarded by the PIF.
▲== Registers ==
'''Table Notation:'''
<pre>
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-n = Default value n at power on
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0480 0000 - SI_DRAM_ADDR
----
{{#invoke:Register table|head|550px|SI_DRAM_ADDR <code>0x0480 0000</code>}}
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| 23-0 | DRAM_ADDR[23:0] | RDRAM address used in SI DMAs
}}
==== <span style="display:none;">0x0480 0004 - SI_PIF_AD_RD64B
----
{{#invoke:Register table|head|550px|SI_PIF_AD_RD64B <code>0x0480 0004</code>}}
{{#invoke:Register table|foot}}
'''TODO'''
==== <span style="display:none;">0x0480 0008 - SI_PIF_AD_WR4B
----
{{#invoke:Register table|head|550px|SI_PIF_AD_WR4B <code>0x0480 0008</code>}}
{{#invoke:Register table|foot}}
'''TODO'''
==== <span style="display:none;">0x0480 0010 - SI_PIF_AD_WR64B
----
{{#invoke:Register table|head|550px|SI_PIF_AD_WR64B <code>0x0480 0010</code>}}
{{#invoke:Register table|foot}}
'''TODO'''
==== <span style="display:none;">0x0480 0014 - SI_PIF_AD_RD4B
----
{{#invoke:Register table|head|550px|SI_PIF_AD_RD4B <code>0x0480 0014</code>}}
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==== <span style="display:none;">0x0480 0018 - SI_STATUS
----
{{#invoke:Register table|head|950px|SI_STATUS <code>0x0480 0018</code>}}
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