Serial Interface: Difference between revisions
→0x0480 0018 - SI_STATUS
(SI_STATUS: PCH_STATE and DMA_STATE are readable, meaning of the read values is currently unknown.) |
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In general, read accesses are blocking, while write accesses are asynchronous. Read accesses while a write is in progress are correctly delayed and run at the end of the write. This is described in detail in [[Memory map#Range 0x1FC0'0000 - 0x1FCF'FFFF (SI external bus)]].
Direct
== DMA transfers ==
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| 11-8 | DMA_STATE[3:0] | Internal DMA state. Non-zero values indicate activity.
| 7-4 | PCH_STATE[3:0] | Internal PIF channel state. Non-zero values indicate activity.
| 3 | DMA_ERROR | Set when overlapping DMA requests occur, or when writing to a misaligned address. Can only be cleared with a power reset.
| 2 | READ_PENDING |
| 1 | IO_BUSY | Set when a direct memory write to PIF_RAM is in progress.
| 0 | DMA_BUSY | Set when a read or write DMA, or an IO write, is in progress.
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