Serial Interface: Difference between revisions
→0x0480 0018 - SI_STATUS
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In general, read accesses are blocking, while write accesses are asynchronous. Read accesses while a write is in progress are correctly delayed and run at the end of the write. This is described in detail in [[Memory map#Range 0x1FC0'0000 - 0x1FCF'FFFF (SI external bus)]].
Direct
== DMA transfers ==
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== Communication protocol with PIF-NUS ==
[[File:SI - PIF communication protocol.gif|thumb|Visual representation of the protocol described in this paragraph]]
The communication protocol with PIF-NUS is the low-level data encapsulation performed by the SI to communicate with PIF-NUS. There are 4 supported packets:
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| 31-13 | Undefined | Initialized to <code>0</code>
| 12 | INTERRUPT | Copy of SI interrupt flag from [[MIPS Interface#0x0430_0008_-_MI_INTERRUPT|MIPS Interface]], which is also seen in the RCP Interrupt Cause register. <br>{{spaces|4}}Writing any value to SI_STATUS clears this bit in all three locations. <br>{{spaces|4}}SI interrupts occur when a DMA finishes.
| 11-8 | DMA_STATE[3:0] | Internal
| 7-4 | PCH_STATE[3:0] | Internal
| 3 | DMA_ERROR | Set when overlapping DMA requests occur, or when writing to a misaligned address. Can only be cleared with a power reset.
| 2 | READ_PENDING |
| 1 | IO_BUSY | Set when a direct memory write to PIF_RAM is in progress.
| 0 | DMA_BUSY | Set when a read or write DMA, or an IO write, is in progress.
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