Serial Interface: Difference between revisions

In general, read accesses are blocking, while write accesses are asynchronous. Read accesses while a write is in progress are correctly delayed and run at the end of the write. This is described in detail in [[Memory map#Range 0x1FC0'0000 - 0x1FCF'FFFF (SI external bus)]].

 

 

== DMA transfers ==

 

== Communication protocol with PIF-NUS ==

The communication protocol with PIF-NUS is the low-level data encapsulation performed by the SI to communicate with PIF-NUS. There are 4 supported packets:

 

* '''RD64B''' (Read 64 bytes): This packet is generated any time the VR4300 issues a DMA read transfer The SI sends on the bus the bits <code>01</code>to identify the packet, followed by bits 10..2 of the address to write (which would normally be <code>111110000</code>, which are bits 10..2 of <code>0x7C0</code>). When the PIF receives this packet, it does not immediately replies with the ACK: first, it runs the joybus handshake described in PIF-RAM, communicating with the various attached devices, and updates the PIF-RAM contents with the result. Only after this is done, the ACK is sent to the SI, followed by the 512 bits of PIF-RAM contents.

* '''WR64B''' (Write 64 bytes). This packet is generated any time the VR4300 issues a DMA write transfer. The SI sends on the bus the bits <code>01</code>to identify the packet, followed by bits 10..2 of the address to write (which would normally be <code>111110000</code>, which are bits 10..2 of <code>0x7C0</code>). The PIF replies with an ACK, and at that point the SI sends the 512-bit sequence to be written to PIF-RAM.

 

== Registers ==

| 31-13 | Undefined | Initialized to <code>0</code>

| 12 | INTERRUPT | Copy of SI interrupt flag from [[MIPS Interface#0x0430_0008_-_MI_INTERRUPT|MIPS Interface]], which is also seen in the RCP Interrupt Cause register. <br>{{spaces|4}}Writing any value to SI_STATUS clears this bit in all three locations. <br>{{spaces|4}}SI interrupts occur when a DMA finishes.

| 1 | IO_BUSY | Set when a direct memory write to PIF_RAM is in progress.

| 0 | DMA_BUSY | Set when a read or write DMA, or an IO write, is in progress.