Serial Interface: Difference between revisions
→0x0480 0018 - SI_STATUS
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In addition to these registers, SI is also in charge of handling the memory mapping of PIF-ROM and PIF-RAM to VR4300. These memories are mapped at physical address <code>0x1FC0 0000</code> (and normally accessed via the uncached segment at <code>0xBFC0 0000</code>).
== Mapped PIF-ROM and PIF-RAM ==▼
When the VR4300 access the physical area at <code>0x1FC0 0000</code> - <code>
The addresses are mapped as follows (and they mirror across the whole area):
== Communication protocol with PIF-NUS ==▼
{| class="wikitable"
The communication protocol with PIF-NUS is the low-level data encapsulation performed by the SI to communicate with PIF-NUS. There are 4 supported packets:▼
|+
|0x000 - 0x7BF
|PIF-ROM. This area contains the IPL1/IPL2 boot code. VR4300 starts running from these addresses after a NMI. During the boot process, PIF-ROM is locked out for security reasons, and during normal runtime all reads from these addresses return 0.
|-
|0x7C0-0x7FF
|PIF-RAM (64 bytes). This area is used to communicate with PIF, mostly to run the Joyous protocol to communicate with external controllers.
|}
Notice that in general the SI is not aware of this memory. For each access to the area, it will issue a read or write request (using the protocol detailed below) which includes the 11-bit address. It does not behave differently depending on the address (eg: writes to the ROM area are still issued).
The SI serial protocol with PIF-NUS only allows to transfer 32-bit words (or 64-byte sequences, when a DMA transfer is requested), so it is advised for the VR4300 to access this memory mapped area only via 32-bit operations. The result obtained when using accesses of different size is detailed in [[Memory map#Range 0x1FC0'0000 - 0x1FCF'FFFF (SI external bus)]].
In general, read accesses are blocking, while write accesses are asynchronous. Read accesses while a write is in progress are correctly delayed and run at the end of the write. This is described in detail in [[Memory map#Range 0x1FC0'0000 - 0x1FCF'FFFF (SI external bus)]].
Direct writes to the memory mapped areas cause interrupts on the VR4300, exactly like DMA transfers. In fact, the two are mostly identical at the hardware level, including the fact that the flag DMA_BUSY is also set.
== DMA transfers ==
The SI allows to transfer the contains of the whole PIF-RAM (64 bytes) with a DMA transfer (both reads and writes). VR4300 can trigger these DMAs by writing to the registers <code>SI_PIF_AD_WR64B</code> and <code>SI_PIF_AD_RD64B</code> (see below).
Notice that the 64-byte read transfer has a special: when the transfer is requested by the SI, the PIF firmware first runs the whole joyous handshake described in PIF-RAM, communicating with the attached device; then t updates the contents of PIF-RAM with the results, and only a this point the ACK is sent to the SI and the actual transfer is done with the updated values. This means that the 64-byte DMA read is usually much slower than expected because it does not just transfer the bytes, but must first wait for the PIF to communicates with all controllers as requested.
▲== Mapped PIF-ROM and PIF-RAM ==
▲When the VR4300 access the physical area at <code>0x1FC0 0000</code> - <code>0x1FC0 0FFF</code>, RCP handles the request via SI; the memory access performed via standard MIPS opcode like LW or SW is converted into a I/O communication with PIF, using the serial bus.
▲== Communication protocol with PIF-NUS ==
[[File:SI - PIF communication protocol.gif|thumb|Visual representation of the protocol described in this paragraph]]
▲The communication protocol with PIF-NUS is the low-level data encapsulation performed by the SI to communicate with PIF-NUS. There are 4 supported packets:
* '''RD4B''' (Read 4 bytes): This packet is generated any time the VR4300 reads from the PIF mapped area. The SI sends on the bus the bits <code>11</code> to identify the packet, followed by bits 10..2 of the address to read (bits 1..0 are assumed to be always 0, that is the address is always 32-bit aligned). The PIF replies with an ACK followed by the 32-bit word that was contained in the memory (ROM or RAM) at the specified address.
* '''WR4B''' (Write 4 bytes): This packet is generated any time the VR4300 writes to the PIF mapped area The SI sends on the bus the bits <code>10</code> to identify the packet, followed by bits 10..2 of the address to write (bits 1..0 are assumed to be always 0, that is the address is always 32-bit aligned). The PIF replies with an ACK, and at that point the SI sends the 32-bit word to be written to memory (RAM; writes to ROM are obviously ignored) at the specified address.
* '''RD64B''' (Read 64 bytes): This packet is generated any time the VR4300 issues a DMA read transfer The SI sends on the bus the bits <code>01</code>to identify the packet, followed by bits 10..2 of the address to write (which would normally be <code>111110000</code>, which are bits 10..2 of <code>0x7C0</code>). When the PIF receives this packet, it does not immediately replies with the ACK: first, it runs the joybus handshake described in PIF-RAM, communicating with the various attached devices, and updates the PIF-RAM contents with the result. Only after this is done, the ACK is sent to the SI, followed by the 512 bits of PIF-RAM contents.
* '''WR64B''' (Write 64 bytes). This packet is generated any time the VR4300 issues a DMA write transfer. The SI sends on the bus the bits <code>01</code>to identify the packet, followed by bits 10..2 of the address to write (which would normally be <code>111110000</code>, which are bits 10..2 of <code>0x7C0</code>). The PIF replies with an ACK, and at that point the SI sends the 512-bit sequence to be written to PIF-RAM.
== Registers ==
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| 31-13 | Undefined | Initialized to <code>0</code>
| 12 | INTERRUPT | Copy of SI interrupt flag from [[MIPS Interface#0x0430_0008_-_MI_INTERRUPT|MIPS Interface]], which is also seen in the RCP Interrupt Cause register. <br>{{spaces|4}}Writing any value to SI_STATUS clears this bit in all three locations. <br>{{spaces|4}}SI interrupts occur when a DMA finishes.
| 11-8 | DMA_STATE[3:0] | Internal
| 7-4 | PCH_STATE[3:0] | Internal
| 3 | DMA_ERROR | Set when overlapping DMA requests occur, or when writing to a misaligned address. Can only be cleared with a power reset.
| 2 | READ_PENDING |
| 1 | IO_BUSY | Set when a direct memory write to PIF_RAM is in progress.
| 0 | DMA_BUSY | Set when a read or write DMA, or an IO write, is in progress.
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