Reality Signal Processor/Interface

The RSP interface is accessed by VR4300 via memory mapped registers at the physical address 0x040x xxxx.

DMEM and IMEM

Both RSP memory banks are fully memory mapped into the VR4300 address space, as follows:

Address range		Memory
0x04000000	0x04000FFF	RSP DMEM
0x04001000	0x04001FFF	RSP IMEM

Access must be performed using 32-bit reads and writes. TODO: document exact behavior on different access sizes.

Since the memory is single-port, it can only be accessed by either the VR4300 or the RSP itself at the same time (including its internal DMA engine). Notice that there is no bus arbiter: an access happening at the same time by both processors will cause problems: typically what happens is that VR4300 wins the race, so the RSP write is lost, or the RSP read returns the same data read by the VR4300 (even if the address was different). Also, if a DMA was in progress, the address of the memory access performed by VR4300 becomes the current address of the DMA transfer, corrupting it. So, in general, VR4300 should access DMEM/IMEM only when RSP is halted.

DMA transfers

DMA transfers can be initiated by either VR4300 or RSP. They can transfer that from/to RDRAM to/from IMEM/DMEM very efficiently, much faster than copying the data word by word using VR4300 over the memory mapped addresses of the memory banks. The speed of transfer is about 4 bytes per VR4300 cycle, or 8 bytes per master clock cycle (plus some small fixed overhead). It is the fastest DMA engine in the N64.

The DMA engine allows to transfer multiple "rows" of data in RDRAM, separated by a "skip" value. This allows for instance to transfer a rectangular portion of a larger image, by specifying the size of each row of the selection portion, the number of rows, and a "skip" value that corresponds to the bytes between the end of a row and the beginning of the following one. Notice that this applies only to RDRAM: accesses in IMEM/DMEM are always linear.

All DMA registers are double-buffered: this means that it is possible to program a DMA transfer while another one is in progress. As soon as the first transfer finishes, the second one will start. The RSP status register reports in separate bits whether there is a transfer ongoing, and whether there is a transfer pending.

RSP Internal Registers

The internal RSP registers are memory mapped into the VR4300 physical address space starting from 0x0404 0000. Normally, accessed are performed through the virtual uncached segment, so at 0xA404 0000.

The exact same physical registers are also exposed as COP0 registers to RSP itself, and can thus be accessed using the MTC0 / MFC0 opcodes.

VR4300 address	RSP COP0 register	Name	Description
0x0404 0000	c0	SP_MEM_ADDR	Address in IMEM/DMEM for a DMA transfer
0x0404 0004	c1	SP_DRAM_ADDR	Address in RDRAM for a DMA transfer
0x0404 0008	c2	SP_RD_LEN	Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM
0x0404 000C	c3	SP_WR_LEN	Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM.

SP_MEM_ADDR

SP_MEM_ADDR 0x0404 0000
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
	—	—	—	—	—	—	—	—
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
	—	—	—	—	—	—	—	—
15:8	U-0	U-0	U-0	RW-0	RW-0	RW-0	RW-0	RW-0
	—			MEM_BANK	MEM_ADDR[11:8]
7:0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	MEM_ADDR[7:0]

bit 31-13	Undefined: Initialized to 0
bit 12	MEM_BANK: Bank accessed by the transfer 0 = DMEM 1 = IMEM
bit 11-0	MEM_ADDR[11:0]: DMEM or IMEM address used in SP DMAs

Extra Details:

MEM_BANK

This bit select the memory bank that will be accessed by the DMA transfer. Notice that, even though the memory banks appear to be contiguous in VR4300 address space, it is not possible to perform a single DMA transfers that spans across two banks. Each transfer will only access a single bank. For instance, to load a microcode, it is normally necessary to do two separate transfers: one for IMEM and one for DMEM.

SP_DRAM_ADDR

SP_DRAM_ADDR 0x0404 0004
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
	—	—	—	—	—	—	—	—
23:16	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	DRAM_ADDR[23:16]
15:8	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	DRAM_ADDR[15:8]
7:0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	DRAM_ADDR[7:0]

bit 31-24	Undefined: Initialized to 0
bit 23-0	DRAM_ADDR[23:0]: RDRAM address used in SP DMAs

RSP PC register

RSP has an internal PC (program counter) register that cannot be explicitly accessed via RSP opcodes. Instead, a memory mapped register is available to VR4300 to control the RSP PC while RSP is halted. The register is called SP_PC.

Notice that VR4300 is allowed to access SP_PC only while RSP is halted. Reading from SP_PC while RSP is running returns garbage data, and writing to it causes RSP to misbehave.

SP_PC

SP_PC 0x0408 0000
31:24	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
	—	—	—	—	—	—	—	—
23:16	U-0	U-0	U-0	U-0	U-0	U-0	U-0	U-0
	—	—	—	—	—	—	—	—
15:8	U-0	U-0	U-0	U-0	RW-0	RW-0	RW-0	RW-0
	—				PC[11:8]
7:0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0	RW-0
	PC[7:0]

bit 31-12	Undefined: Initialized to 0
bit 21-0	PC[21:0]: Read/write the RSP PC (program counter)

Extra Details:

PC

Reads while RSP is running returns random bits. Reads while RSP is halted return the address of the instruction that the RSP will execute when it is unhalted.
Writes will also reset the RSP CPU core pipeline, so any pending writeback or branch are discarded.