Reality Signal Processor/Interface: Difference between revisions
No edit summary |
|||
Line 23: | Line 23: | ||
The exact same physical registers are also exposed as COP0 registers to RSP itself, and can thus be accessed using the MTC0 / MFC0 opcodes. |
The exact same physical registers are also exposed as COP0 registers to RSP itself, and can thus be accessed using the MTC0 / MFC0 opcodes. |
||
{| class="wikitable" |
|||
|+ |
|||
!VR4300 address |
|||
!RSP COP0 register |
|||
!Name |
|||
!Description |
|||
|- |
|||
|0x0404 0000 |
|||
|c0 |
|||
|SP_MEM_ADDR |
|||
|Address in IMEM/DMEM for a DMA transfer |
|||
|- |
|||
|0x0404 0004 |
|||
|c1 |
|||
|SP_DRAM_ADDR |
|||
|Address in RDRAM for a DMA transfer |
|||
|- |
|||
|0x0404 0008 |
|||
|c2 |
|||
|SP_RD_LEN |
|||
|Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM |
|||
|- |
|||
|0x0404 000C |
|||
|c3 |
|||
|SP_WR_LEN |
|||
|Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM. |
|||
|} |
|||
==== Register details ==== |
|||
----{{#invoke:Register table|head|850px|SP_MEM_ADDR <code>0x0404 0000</code>}} |
----{{#invoke:Register table|head|850px|SP_MEM_ADDR <code>0x0404 0000</code>}} |
||
{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
Revision as of 20:57, 27 March 2022
The RSP interface is accessed by VR4300 via memory mapped registers at the physical address 0x040x xxxx.
DMEM and IMEM
Both RSP memory banks are fully memory mapped into the VR4300 address space, as follows:
Address range | Memory | |
---|---|---|
0x04000000 | 0x04000FFF | RSP DMEM |
0x04001000 | 0x04001FFF | RSP IMEM |
Access must be performed using 32-bit reads and writes. TODO: document exact behavior on different access sizes.
Since the memory is single-port, it can only be accessed by either the VR4300 or the RSP itself at the same time (including its internal DMA engine). Notice that there is no bus arbiter: an access happening at the same time by both processors will cause problems: typically what happens is that VR4300 wins the race, so the RSP write is lost, or the RSP read returns the same data read by the VR4300 (even if the address was different). Also, if a DMA was in progress, the address of the memory access performed by VR4300 becomes the current address of the DMA transfer, corrupting it. So, in general, VR4300 should access DMEM/IMEM only when RSP is halted.
RSP Internal Registers
The internal RSP registers are memory mapped into the VR4300 physical address space starting from 0x0404 0000. Normally, accessed are performed through the virtual uncached segment, so at 0xA404 0000.
The exact same physical registers are also exposed as COP0 registers to RSP itself, and can thus be accessed using the MTC0 / MFC0 opcodes.
VR4300 address | RSP COP0 register | Name | Description |
---|---|---|---|
0x0404 0000 | c0 | SP_MEM_ADDR | Address in IMEM/DMEM for a DMA transfer |
0x0404 0004 | c1 | SP_DRAM_ADDR | Address in RDRAM for a DMA transfer |
0x0404 0008 | c2 | SP_RD_LEN | Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM |
0x0404 000C | c3 | SP_WR_LEN | Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM. |
Register details
SP_MEM_ADDR 0x0404 0000
| ||||||||
---|---|---|---|---|---|---|---|---|
31:24 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
— | — | — | — | — | — | — | — | |
23:16 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
— | — | — | — | — | — | — | — | |
15:8 | U-0 | U-0 | U-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
- | MEM_BANK | MEM_ADDR[11:8] | ||||||
7:0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
MEM_ADDR[7:0] |
bit 31-13 | Undefined: Initialized to 0
|
bit 12 | MEM_BANK: Bank accessed by the transfer 0 = DMEM 1 = IMEM |
bit 11-0 | MEM_ADDR[11:0]: DMEM or IMEM address used in SP DMAs |
Extra Details:
- MEM_BANK
- This bit select the memory bank that will be accessed by the DMA transfer. Notice that, even though the memory banks appear to be contiguous in VR4300 address space, it is not possible to perform a single DMA transfers that spans across two banks. Each transfer will only access a single bank. For instance, to load a microcode, it is normally necessary to do two separate transfers: one for IMEM and one for DMEM.
SP_DRAM_ADDR 0x0404 0004
| ||||||||
---|---|---|---|---|---|---|---|---|
31:24 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 | U-0 |
— | — | — | — | — | — | — | — | |
23:16 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
DRAM_ADDR[23:16] | ||||||||
15:8 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
DRAM_ADDR[15:8] | ||||||||
7:0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 | RW-0 |
DRAM_ADDR[7:0] |
bit 31-24 | Undefined: Initialized to 0
|
bit 23-0 | DRAM_ADDR[23:0]: RDRAM address used in SP DMAs |