Reality Signal Processor/Interface: Difference between revisions
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|0x0404 0000 |
|0x0404 0000 |
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|style="text-align: center;" |c0 |
|style="text-align: center;" |c0 |
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|SP_DMA_SPADDR |
|[[Reality Signal Processor/Interface#SP DMA SPADDR|SP_DMA_SPADDR]] |
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|Address in IMEM/DMEM for a DMA transfer |
|Address in IMEM/DMEM for a DMA transfer |
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|0x0404 0004 |
|0x0404 0004 |
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|style="text-align: center;" |c1 |
|style="text-align: center;" |c1 |
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|SP_DMA_RAMADDR |
|[[Reality Signal Processor/Interface#SP DMA RAMADDR|SP_DMA_RAMADDR]] |
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|Address in RDRAM for a DMA transfer |
|Address in RDRAM for a DMA transfer |
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|0x0404 0008 |
|0x0404 0008 |
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|style="text-align: center;" |c2 |
|style="text-align: center;" |c2 |
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|[[Reality Signal Processor/Interface#SP DMA RDLEN|SP_DMA_RDLEN]] |
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|SP_DMA_RDLEN |
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|Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM |
|Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM |
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|0x0404 000C |
|0x0404 000C |
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|style="text-align: center;" |c3 |
|style="text-align: center;" |c3 |
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|[[Reality Signal Processor/Interface#SP DMA WRLEN|SP_DMA_WRLEN]] |
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|SP_DMA_WRLEN |
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|Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM. |
|Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM. |
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|0x0404 0010 |
|0x0404 0010 |
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|style="text-align: center;" |c4 |
|style="text-align: center;" |c4 |
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|[[Reality Signal Processor/Interface#SP STATUS|SP_STATUS]] |
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|SP_STATUS |
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|RSP status register. |
|RSP status register. |
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|0x0404 0014 |
|0x0404 0014 |
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|style="text-align: center;" |c5 |
|style="text-align: center;" |c5 |
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|[[Reality Signal Processor/Interface#SP DMA FULL|SP_DMA_FULL]] |
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|SP_DMA_FULL |
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|Report whether there is a pending DMA transfer (mirror of <code>DMA_FULL</code> bit of SP_STATUS) |
|Report whether there is a pending DMA transfer (mirror of <code>DMA_FULL</code> bit of SP_STATUS) |
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|0x0404 0018 |
|0x0404 0018 |
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|style="text-align: center;" |c6 |
|style="text-align: center;" |c6 |
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|[[Reality Signal Processor/Interface#SP DMA BUSY|SP_DMA_BUSY]] |
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|SP_DMA_BUSY |
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|Report whether there is a DMA transfer in progress (mirror of <code>DMA_BUSY</code> bit of SP_STATUS) |
|Report whether there is a DMA transfer in progress (mirror of <code>DMA_BUSY</code> bit of SP_STATUS) |
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|0x0404 001C |
|0x0404 001C |
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|style="text-align: center;" |c7 |
|style="text-align: center;" |c7 |
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|[[Reality Signal Processor/Interface#SP SEMAPHORE|SP_SEMAPHORE]] |
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|SP_SEMAPHORE |
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|Register to assist implementing a simple mutex between VR4300 and RSP. |
|Register to assist implementing a simple mutex between VR4300 and RSP. |
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