Reality Signal Processor/Interface: Difference between revisions

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|-
|-
|0x0404 0000
|0x0404 0000
|style="text-align: center;" |c0
|c0
|SP_DMA_SPADDR
|SP_DMA_SPADDR
|Address in IMEM/DMEM for a DMA transfer
|Address in IMEM/DMEM for a DMA transfer
|-
|-
|0x0404 0004
|0x0404 0004
|style="text-align: center;" |c1
|c1
|SP_DMA_RAMADDR
|SP_DMA_RAMADDR
|Address in RDRAM for a DMA transfer
|Address in RDRAM for a DMA transfer
|-
|-
|0x0404 0008
|0x0404 0008
|style="text-align: center;" |c2
|c2
|SP_DMA_RDLEN
|SP_DMA_RDLEN
|Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM
|Length of a DMA transfer. Writing this register triggers a DMA transfer from RDRAM to IMEM/DMEM
|-
|-
|0x0404 000C
|0x0404 000C
|style="text-align: center;" |c3
|c3
|SP_DMA_WRLEN
|SP_DMA_WRLEN
|Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM.
|Length of a DMA transfer. Writing this register triggers a DMA transfer from IMEM/DMEM to RDRAM.
|-
|-
|0x0404 0010
|0x0404 0010
|style="text-align: center;" |c4
|c4
|SP_STATUS
|SP_STATUS
|RSP status register.
|RSP status register.
|-
|-
|0x0404 0014
|0x0404 0014
|style="text-align: center;" |c5
|c5
|SP_DMA_FULL
|SP_DMA_FULL
|Report whether there is a pending DMA transfer (mirror of <code>DMA_FULL</code> bit of SP_STATUS)
|Report whether there is a pending DMA transfer (mirror of <code>DMA_FULL</code> bit of SP_STATUS)
|-
|-
|0x0404 0018
|0x0404 0018
|style="text-align: center;" |c6
|c6
|SP_DMA_BUSY
|SP_DMA_BUSY
|Report whether there is a DMA transfer in progress (mirror of <code>DMA_BUSY</code> bit of SP_STATUS)
|Report whether there is a DMA transfer in progress (mirror of <code>DMA_BUSY</code> bit of SP_STATUS)
|-
|-
|0x0404 001C
|0x0404 001C
|style="text-align: center;" |c7
|c7
|SP_SEMAPHORE
|SP_SEMAPHORE
|Register to assist implementing a simple mutex between VR4300 and RSP.
|Register to assist implementing a simple mutex between VR4300 and RSP.