Reality Signal Processor/Interface: Difference between revisions

DMA transfers only happen between 8-byte aligned addresses (in both RDRAM and IMEM/DMEM). DMA registers do not allow misaligned addresses to be written, as the lowest 3 bits are ignored and fixed to 0. The same applies to the length registers, so that the transfer size is always a multiple of 8.

|SP_DMA_SPADDR

|SP_DMA_RAMADDR

|SP_DMA_RDLEN

|SP_DMA_WRLEN

=== SP_DMA_SPADDR ===

{{#invoke:Register table|head|850px|SP_DMA_SPADDR <code>0x0404 0000</code> (RSP COP0: <code>c0</code>)}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0

| colspan="5" | MEM_ADDR[7:3] || 0 || 0 || 0

| 11-0 | MEM_ADDR[11:0] | DMEM or IMEM address used in SP DMAs. Notice that the lowest 3 bits are always 0.

:: This bit selects the memory bank that will be accessed by the DMA transfer. Notice that, even though the memory banks appear to be contiguous in VR4300 address space, it is not possible to perform a single DMA transfers that spans across two banks. Each transfer will only access a single bank. For instance, to load a microcode, it is normally necessary to do two separate transfers: one for IMEM and one for DMEM.

: '''MEM_ADDR'''

:: This field contains the address in SP memory where the DMA transfer begins. The address is always aligned to 8 bytes, as the lowest 3 bits cannot be written. Notice that after writing to this register, the value is latched by SP but it is kept "pending" until the transfer is initiated via writes to <code>SP_DMA_WRLEN</code> or <code>SP_DMA_RDLEN</code>. Reads will continue returning the current (non-pending) value that refers to either an ongoing DMA transfer, or the last finished one. After a DMA transfer is finished, reading this register contains the address after the last one that was written.

=== SP_DMA_RAMADDR ===

{{#invoke:Register table|head|550px|SP_DMA_RAMADDR <code>0x0404 0004</code> (RSP COP0: <code>c1</code>)}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0

| colspan="5" | DRAM_ADDR[7:3] || 0 || 0 || 0

| 23-0 | DRAM_ADDR[23:0] | RDRAM address used in SP DMAs. Notice that the lowest 3 bits are always 0.

'''Extra Details:'''

: '''MEM_ADDR'''

:: This field contains the address in RDRAM memory where the DMA transfer begins. The address is always aligned to 8 bytes, as the lowest 3 bits cannot be written. Notice that after writing to this register, the value is latched by SP but it is kept "pending" until the transfer is initiated via writes to <code>SP_DMA_WRLEN</code> or <code>SP_DMA_RDLEN</code>. Reads will continue returning the current (non-pending) value that refers to either an ongoing DMA transfer, or the last finished one. After a DMA transfer is finished, reading this register contains the address after the last one that was written.

=== SP_DMA_RDLEN ===

This register is used to initiate a DMA transfer from RDRAM to DMEM/IMEM. It must be written as third register, after programming <code>SP_DMA_SPADDR</code> and <code>SP_DMA_RAMADDR</code>. As soon as it is written, if the DMA engine was idle, a DMA transfer is started. Otherwise, the DMA transfer is enqueued (double-buffered), waiting for the previous one to be finished.

{{#invoke:Register table|head|550px|SP_DMA_RDLEN <code>0x0404 0008</code> (RSP COP0: <code>c2</code>)}}

{{#invoke:Register table|row|31:24}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0

|-

| colspan="8" | SKIP[11:4]

{{#invoke:Register table|row|23:16}}

| RW-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0

|-

| SKIP[3] || 0 || 0 || 0 || colspan="4" | COUNT[7:4]

{{#invoke:Register table|row|15:8}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0

|-

| colspan="4" | COUNT[3:0] || colspan="4" | LEN[11:8]

{{#invoke:Register table|row|7:0}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0

|-

| colspan="5" | LEN[7:3] || 0 || 0 || 0

{{#invoke:Register table|foot}}{{#invoke:Register table|definitions

| 31-20 | SKIP | Number of bytes to skip in RDRAM after each row. Notice that the lowest 3 bits are always 0.

| 19-12 | COUNT | Number of rows to transfer minus 1.

| 21-0 | RDLEN | Number of bytes to transfer for each row minus 1. Notice that the lowest 3 bits are always 0.

}}

'''Extra Details:'''

: '''RDLEN'''

:: Like other DMA transfers in N64, this field holds the number of bytes to transfer minus 1. Since the DMA engine works in 64-bit words, writing 0 (or any value up to and including 6) starts a transfer of exactly 8 bytes. After the transfer is finished, this field contains <code>0xFF8</code> (which would be -8, as expected for a transfer in units of 8 bytes).

: '''COUNT and SKIP'''

:: Setting <code>COUNT</code> to 0 initiates a linear transfer of <code>RDLEN</code> plus 1 bytes (rounded up to 8 bytes); in this case, the value of <code>SKIP</code> is effectively ignored as only one row is transferred. With any other value, <code>COUNT</code> indicates the number of rows, to transfer a portion of a rectangular image, and <code>SKIP</code> indicates the so-called row stride, that is number of bytes to add to jump from the end of a row to the beginning of next one. After a DMA transfer is finished, <code>COUNT</code> is reset to 0, and <code>SKIP</code> is unchanged.

=== SP_DMA_WRLEN ===

This register is used to initiate a DMA transfer from DMEM/IMEM to RDRAM. It must be written as third register, after programming <code>SP_DMA_SPADDR</code> and <code>SP_DMA_RAMADDR</code>. As soon as it is written, if the DMA engine was idle, a DMA transfer is started. Otherwise, the DMA transfer is enqueued (double-buffered), waiting for the previous one to be finished.

{{#invoke:Register table|head|550px|SP_DMA_WRLEN <code>0x0404 000C</code> (RSP COP0: <code>c3</code>)}}

{{#invoke:Register table|row|31:24}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0

|-

| colspan="8" | SKIP[11:4]

{{#invoke:Register table|row|23:16}}

| RW-0 || U-0 || U-0 || U-0 || RW-0 || RW-0 || RW-0 || RW-0

|-

| SKIP[3] || 0 || 0 || 0 || colspan="4" | COUNT[7:4]

{{#invoke:Register table|row|15:8}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0

|-

| colspan="4" | COUNT[3:0] || colspan="4" | LEN[11:8]

{{#invoke:Register table|row|7:0}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0

|-

| colspan="5" | LEN[7:3] || 0 || 0 || 0

{{#invoke:Register table|foot}}{{#invoke:Register table|definitions

| 31-20 | SKIP | Number of bytes to skip in RDRAM after each row. Notice that the lowest 3 bits are always 0.

| 19-12 | COUNT | Number of rows to transfer minus 1.

| 21-0 | RDLEN | Number of bytes to transfer for each row minus 1. Notice that the lowest 3 bits are always 0.

}}

'''Extra Details:'''

Please refer to <code>SP_DMA_RDLEN</code> for details.