Reality Display Processor/Interface: Difference between revisions

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(Some DPS_TEST_MODE and related)
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====<span style="display:none;">0x0420 0004 - DPS_TEST_MODE ====
====<span style="display:none;">0x0420 0004 - DPS_TEST_MODE ====
----
----{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}}

'''When Reading:'''

{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}}
{{#invoke:Register table|row|31:24}}
| colspan="4" | U-4 || colspan="4" | R-4
|-
| colspan="4" | 0 || colspan="4" | cspan0[3:0]
{{#invoke:Register table|row|23:16}}
| colspan="4" | R-4 || colspan="4" | R-4
|-
| colspan="4" | cspan1[3:0] || colspan="4" | zspan0[3:0]
{{#invoke:Register table|row|15:8}}
| colspan="4" | R-4 || U-? || U-? || U-? || U-?
|-
| colspan="4" | zspan1[3:0] || ? || ? || ? || ?
{{#invoke:Register table|row|7:0}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || R-1
|-
| 1 || ? || ? || ? || ? || 1 || ? || TEST_ENABLE
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-28 | 0 | Always 0?
| 27-24 | cspan0[3:0] | Color span counter? Increments (and potentially overflows) based on how many 16-byte segments a drawn primitive covers.
| 23-20 | cspan1[3:0] | Color span counter? Synced with the other counter; if the other counter has the msbit unset this one has it set and vice-versa.
| 19-16 | zspan0[3:0] | Depth span counter? Increments (and potentially overflows) based on how many 16-byte segments a drawn primitive covers, only when depth read or write is enabled.
| 15-12 | zspan1[3:0] | Depth span counter? Synced with the other counter; if the other counter has the msbit unset this one has it set and vice-versa.
| 7 | 1 | Always 1?
| 2 | 1 | Always 1?
| 0 | TEST_ENABLE | Whether span buffer testing is enabled.
}}

'''When Writing:'''

{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}}
{{#invoke:Register table|row|31:24}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
Line 383: Line 418:
| — || — || — || — || — || — || — || —
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || RW-?
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || W-1
|-
|-
| — || — || — || — || — || — || — || ENABLE
| — || — || — || — || — || — || — || TEST_ENABLE
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 0 | TEST_ENABLE | Enables span buffer test access via '''DPS_BUFTEST_ADDR''' and '''DPS_BUFTEST_DATA'''. '''Warning:''' If the span test mode is used the RDP should be idle, else the RDP may hang.
| 0 | ENABLE | ?
}}
}}

====<span style="display:none;">0x0420 0008 - DPS_BUFTEST_ADDR ====
====<span style="display:none;">0x0420 0008 - DPS_BUFTEST_ADDR ====
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_ADDR <code>0x0420 0008</code>}}
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_ADDR <code>0x0420 0008</code>}}
{{#invoke:Register table|row|31:24}}
{{#invoke:Register table|row|31:24}}
| colspan="8" | U-8
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
|-
| colspan="8" | —
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
{{#invoke:Register table|row|23:16}}
| colspan="8" | U-8
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
|-
| colspan="8" | —
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
{{#invoke:Register table|row|15:8}}
| colspan="8" | U-8
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
|-
| colspan="8" | —
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| U-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
| U-1 || colspan="7" | RW-7
|-
|-
| — || colspan=7| ADDRESS[6:0]
| — || colspan=7| ADDRESS[6:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 6-0 | ADDRESS[6:0] | ?
| 6-0 | ADDRESS[6:0] | Sets the span buffer word address that '''DPS_BUFTEST_DATA''' will read from or write to.
}}
}}

Span buffers are 288 bytes of memory while a 7-bit word index can address up to 512 bytes; when some addresses are read/written with '''DPS_BUFTEST_DATA''' some bits are fixed to 0. The span buffer data is arrayed such that 72 bits are accessed over 4 word addresses. The data layout is shown below, the first two columns can contain color/depth/texture data while the third column can contain coverage.
<pre>
| 0 1 2 3
----+------------------------------------
0 | XXXXXXXX XXXXXXXX 000000XX 00000000
4 | XXXXXXXX XXXXXXXX 000000XX 00000000
8 | XXXXXXXX XXXXXXXX 000000XX 00000000
C | XXXXXXXX XXXXXXXX 000000XX 00000000
10 | XXXXXXXX XXXXXXXX 000000XX 00000000
14 | XXXXXXXX XXXXXXXX 000000XX 00000000
18 | XXXXXXXX XXXXXXXX 000000XX 00000000
1C | XXXXXXXX XXXXXXXX 000000XX 00000000
20 | XXXXXXXX XXXXXXXX 000000XX 00000000
24 | XXXXXXXX XXXXXXXX 000000XX 00000000
28 | XXXXXXXX XXXXXXXX 000000XX 00000000
2C | XXXXXXXX XXXXXXXX 000000XX 00000000
30 | XXXXXXXX XXXXXXXX 000000XX 00000000
34 | XXXXXXXX XXXXXXXX 000000XX 00000000
38 | XXXXXXXX XXXXXXXX 000000XX 00000000
3C | XXXXXXXX XXXXXXXX 000000XX 00000000
40 | XXXXXXXX XXXXXXXX 000000XX 00000000
44 | XXXXXXXX XXXXXXXX 000000XX 00000000
48 | XXXXXXXX XXXXXXXX 000000XX 00000000
4C | XXXXXXXX XXXXXXXX 000000XX 00000000
50 | XXXXXXXX XXXXXXXX 000000XX 00000000
54 | XXXXXXXX XXXXXXXX 000000XX 00000000
58 | XXXXXXXX XXXXXXXX 000000XX 00000000
5C | XXXXXXXX XXXXXXXX 000000XX 00000000
60 | XXXXXXXX XXXXXXXX 000000XX 00000000
64 | XXXXXXXX XXXXXXXX 000000XX 00000000
68 | XXXXXXXX XXXXXXXX 000000XX 00000000
6C | XXXXXXXX XXXXXXXX 000000XX 00000000
70 | XXXXXXXX XXXXXXXX 000000XX 00000000
74 | XXXXXXXX XXXXXXXX 000000XX 00000000
78 | XXXXXXXX XXXXXXXX 000000XX 00000000
7C | XXXXXXXX XXXXXXXX 000000XX 00000000
</pre>

====<span style="display:none;">0x0410 000C - DPS_BUFTEST_DATA ====
====<span style="display:none;">0x0410 000C - DPS_BUFTEST_DATA ====
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_DATA <code>0x0420 000C</code>}}
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_DATA <code>0x0420 000C</code>}}
{{#invoke:Register table|row|31:24}}
{{#invoke:Register table|row|31:24}}
| colspan="8" | RW-8
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
|-
| colspan=8|DATA[31:24]
| colspan=8|DATA[31:24]
{{#invoke:Register table|row|23:16}}
{{#invoke:Register table|row|23:16}}
| colspan="8" | RW-8
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
|-
| colspan=8|DATA[23:16]
| colspan=8|DATA[23:16]
{{#invoke:Register table|row|15:8}}
{{#invoke:Register table|row|15:8}}
| colspan="8" | RW-8
| RW-? || RW-? || RW-? || RW-? || RW-? || RW- || RW-? || RW-?
|-
|-
| colspan=8|DATA[15:0]
| colspan=8|DATA[15:0]
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| colspan="8" | RW-8
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
|-
| colspan=8|DATA[7:0]
| colspan=8|DATA[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
{{#invoke:Register table|definitions
| 31-0 | DATA | Reading from this register reads the span buffer data at the current '''DPS_BUFTEST_ADDR'''. Writing to this register sets the span buffer data at the current '''DPS_BUFTEST_ADDR''' to the write value.
| 31-0 | DATA | ?
}}
}}

This register requires span buffer test access to be enabled in '''DPS_TEST_MODE_REG''' to be functional.
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