Reality Display Processor/Interface: Difference between revisions
→0x0410 0014 (c13) - DPC_BUF_BUSY
(revert misunderstanding of "initial state" fields) |
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:'''CLOCK''' This register accesses a read-only 24-bit clock that runs at the RCP frequency (which is 62.5 Mhz on standard N64, and 96 Mhz on iQue). The counter starts ticking from boot and does not stop (not even if you freeze the RDP via the `FREEZE` bit in `DPC_STATUS`). The only possible interaction from the CPU/RSP is to reset it to 0 by writing the `CLR_CLOCK` bit in `DPC_STATUS`. Being the only counter available directly from RSP, it can be useful to perform benchmarks on it.
====<span style="display:none;">0x0410 0014 (c13) -
----{{#invoke:Register table|head|1200px|
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
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| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
| colspan=8|
{{#invoke:Register table|row|15:8}}
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
| colspan=8|
{{#invoke:Register table|row|7:0}}
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
| colspan=8|
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 23-0 |
}}
'''Extra Details:'''
:'''CMD_BUSY''' This register accesses a read-only 24-bit clock that counts up any RCP cycle in which the internal RDP command FIFO is not empty. The FIFO is filled via RDP DMA with new commands, and is flushed as commands get executed, so this counter is the closest thing to a "RDP activity counter".
====<span style="display:none;">0x0410 0018 (c14) - DPC_PIPE_BUSY ====
----{{#invoke:Register table|head|1200px|DPC_PIPE_BUSY <code>0x0410 0018</code> (<code>c14</code>)}}
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