Reality Display Processor/Interface: Difference between revisions

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VisualWikitext
(START_GCLK description)
(revert misunderstanding of "initial state" fields)
Line 375: Line 375:
{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}}
{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}}
{{#invoke:Register table|row|31:24}}
{{#invoke:Register table|row|31:24}}
| colspan="4" | U-4 || colspan="4" | R-4
| U-0 || U-0 || U-0 || U-0 || R-? || R-? || R-? || R-?
|-
|-
| colspan="4" | 0 || colspan="4" | cspan0[3:0]
| colspan="4" | 0 || colspan="4" | cspan0[3:0]
{{#invoke:Register table|row|23:16}}
{{#invoke:Register table|row|23:16}}
| colspan="4" | R-4 || colspan="4" | R-4
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
|-
| colspan="4" | cspan1[3:0] || colspan="4" | zspan0[3:0]
| colspan="4" | cspan1[3:0] || colspan="4" | zspan0[3:0]
{{#invoke:Register table|row|15:8}}
{{#invoke:Register table|row|15:8}}
| colspan="4" | R-4 || U-? || U-? || U-? || U-?
| R-? || R-? || R-? || R-? || U-? || U-? || U-? || U-?
|-
|-
| colspan="4" | zspan1[3:0] || ? || ? || ? || ?
| colspan="4" | zspan1[3:0] || ? || ? || ? || ?
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || R-1
| U-1 || U-? || U-? || U-? || U-? || U-1 || U-? || R-1
|-
|-
| 1 || ? || ? || ? || ? || 1 || ? || TEST_ENABLE
| 1 || ? || ? || ? || ? || 1 || ? || TEST_ENABLE
Line 429: Line 429:
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_ADDR <code>0x0420 0008</code>}}
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_ADDR <code>0x0420 0008</code>}}
{{#invoke:Register table|row|31:24}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
| colspan="8" | U-8
|-
|-
| colspan="8" | —
| colspan="8" | —
{{#invoke:Register table|row|23:16}}
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
| colspan="8" | U-8
|-
|-
| colspan="8" | —
| colspan="8" | —
{{#invoke:Register table|row|15:8}}
{{#invoke:Register table|row|15:8}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
| colspan="8" | U-8
|-
|-
| colspan="8" | —
| colspan="8" | —
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| U-1 || colspan="7" | RW-7
| U-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
|-
| — || colspan=7| ADDRESS[6:0]
| — || colspan=7| ADDRESS[6:0]
Line 490: Line 490:
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_DATA <code>0x0420 000C</code>}}
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_DATA <code>0x0420 000C</code>}}
{{#invoke:Register table|row|31:24}}
{{#invoke:Register table|row|31:24}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
| colspan="8" | RW-8
|-
|-
| colspan=8|DATA[31:24]
| colspan=8|DATA[31:24]
{{#invoke:Register table|row|23:16}}
{{#invoke:Register table|row|23:16}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
| colspan="8" | RW-8
|-
|-
| colspan=8|DATA[23:16]
| colspan=8|DATA[23:16]
{{#invoke:Register table|row|15:8}}
{{#invoke:Register table|row|15:8}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
| colspan="8" | RW-8
|-
|-
| colspan=8|DATA[15:0]
| colspan=8|DATA[15:0]
{{#invoke:Register table|row|7:0}}
{{#invoke:Register table|row|7:0}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
| colspan="8" | RW-8
|-
|-
| colspan=8|DATA[7:0]
| colspan=8|DATA[7:0]
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