Reality Display Processor/Interface: Difference between revisions
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(START_GCLK description) |
(revert misunderstanding of "initial state" fields) |
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Line 375: | Line 375: | ||
{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}} |
{{#invoke:Register table|head|1200px|DPS_TEST_MODE <code>0x0420 0004</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| U-0 || U-0 || U-0 || U-0 || R-? || R-? || R-? || R-? |
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| colspan="4" | 0 || colspan="4" | cspan0[3:0] |
| colspan="4" | 0 || colspan="4" | cspan0[3:0] |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-? |
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| colspan="4" | cspan1[3:0] || colspan="4" | zspan0[3:0] |
| colspan="4" | cspan1[3:0] || colspan="4" | zspan0[3:0] |
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{{#invoke:Register table|row|15:8}} |
{{#invoke:Register table|row|15:8}} |
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| R-? || R-? || R-? || R-? || U-? || U-? || U-? || U-? |
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| colspan="4" | zspan1[3:0] || ? || ? || ? || ? |
| colspan="4" | zspan1[3:0] || ? || ? || ? || ? |
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{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| U- |
| U-1 || U-? || U-? || U-? || U-? || U-1 || U-? || R-1 |
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| 1 || ? || ? || ? || ? || 1 || ? || TEST_ENABLE |
| 1 || ? || ? || ? || ? || 1 || ? || TEST_ENABLE |
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Line 429: | Line 429: | ||
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_ADDR <code>0x0420 0008</code>}} |
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_ADDR <code>0x0420 0008</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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| colspan="8" | U-8 |
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| colspan="8" | — |
| colspan="8" | — |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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| colspan="8" | U-8 |
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|- |
|- |
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| colspan="8" | — |
| colspan="8" | — |
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{{#invoke:Register table|row|15:8}} |
{{#invoke:Register table|row|15:8}} |
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| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-? |
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| colspan="8" | U-8 |
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| colspan="8" | — |
| colspan="8" | — |
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{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| U- |
| U-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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| — || colspan=7| ADDRESS[6:0] |
| — || colspan=7| ADDRESS[6:0] |
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Line 490: | Line 490: | ||
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_DATA <code>0x0420 000C</code>}} |
----{{#invoke:Register table|head|1200px|DPS_BUFTEST_DATA <code>0x0420 000C</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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| colspan="8" | RW-8 |
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| colspan=8|DATA[31:24] |
| colspan=8|DATA[31:24] |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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| colspan="8" | RW-8 |
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| colspan=8|DATA[23:16] |
| colspan=8|DATA[23:16] |
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{{#invoke:Register table|row|15:8}} |
{{#invoke:Register table|row|15:8}} |
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| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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| colspan="8" | RW-8 |
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| colspan=8|DATA[15:0] |
| colspan=8|DATA[15:0] |
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{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? |
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| colspan="8" | RW-8 |
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| colspan=8|DATA[7:0] |
| colspan=8|DATA[7:0] |