Reality Display Processor/Commands: Difference between revisions
Sync Load/Pipe/Tile/Full
(Set Key R/GB) |
(Sync Load/Pipe/Tile/Full) |
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====<span style="display:none;">0x26 -
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{| class="wikitable" style="text-align: center; white-space:nowrap;"
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| 63:48 || — || — || colspan=6| command = 0x26[5:0] || — || — || — || — || — || — || — || —
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Stalls the RDP pipeline for exactly 25 GCLK cycles. This guarantees that the loading pipeline will be available for use following any prior operation.
====<span style="display:none;">0x27 - Sync_Pipe ====▼
The stall is always 25 cycles and does not wait on any particular internal signal(s), if a Sync Load is queued when it is not needed it simply wastes the full length of time.
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{| class="wikitable" style="text-align: center; white-space:nowrap;"
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| 63:48 || — || — || colspan=6| command = 0x27[5:0] || — || — || — || — || — || — || — || —
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Stalls the RDP pipeline for exactly 50 GCLK cycles. This guarantees that any preceding primitives will be fully rendered and it is safe to modify rendering attributes such as color registers, othermodes and combine mode.
====<span style="display:none;">0x28 - Sync_Tile ====▼
The stall is always 50 cycles and does not wait on any particular internal signal(s), if a Sync Pipe is queued when it is not needed it simply wastes the full length of time.
(TOVERIFY/Speculation: Changing an attribute without a sync typically corrupts only up to at most 24 pixels of the last primitive, suggesting the RDP pixel pipeline is ~24 cycles deep. Can a tile sync account for all or at least almost all attribute changes?)
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{| class="wikitable" style="text-align: center; white-space:nowrap;"
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| 63:48 || — || — || colspan=6| command = 0x28[5:0] || — || — || — || — || — || — || — || —
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Stalls the RDP pipeline for exactly 33 GCLK cycles. This guarantees that any preceding primitives will have finished using tile information and that it is now safe to modify tile descriptors without affecting prior primitives.
====<span style="display:none;">0x29 - Sync_Full ====▼
The stall is always 33 cycles and does not wait on any particular internal signal(s), if a Sync Tile is queued when it is not needed it simply wastes the full length of time.
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{| class="wikitable" style="text-align: center; white-space:nowrap;"
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| 63:48 || — || — || colspan=6| command = 0x29[5:0] || — || — || — || — || — || — || — || —
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| 61:56 | command[5:0] | 0x29
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Waits for all currently staged pipeline and memory operations to complete before halting the RDP pipeline counter and raising the DP interrupt in the [[MIPS Interface]].
'''Hazards'''
* Ensure this is the final command consumed before hitting DP_END, otherwise the RDP may hang.
====<span style="display:none;">0x2a - Set Key GB ====
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