RDRAM Interface: Difference between revisions

RDRAM Interface (view source)

Revision as of 02:25, 4 November 2023

74 bytes added , 6 months ago

RI_REFRESH: Emphasize that "refresh enable" refers specifically to the automatic refresh issued on VI HSYNC, other small tweaks.

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Tharo

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Revision as of 00:49, 4 November 2023 (view source) Tharo (talk \| contribs) (RI_SELECT: Partial research into the set of allowed configurations) ← Older edit		Revision as of 02:25, 4 November 2023 (view source) Tharo (talk \| contribs) (RI_REFRESH: Emphasize that "refresh enable" refers specifically to the automatic refresh issued on VI HSYNC, other small tweaks.) Newer edit →
Line 160: \| ??-19\| MultiBank[3:0] \| Bitfield indicating multibank RDRAM modules. Up to four multibank modules are tracked, enough to fill 8MiB with 4x2MiB modules. <br>Probably why RDRAM modules are re-ordered with multibanks modules first during initialization in IPL3. \| 18 \| Opt \| Optimize. Usually set to <code>0x1</code>. \| 17 \| En \| Automatic Refresh Enable. Usually set to <code>0x1</code>. \| 16 \| Bank \| ~~Usually~~Oscillates ~~set~~between to0 ~~<code>0x0</code>~~and 1 during operation. \| 15-8 \| DirtyRefreshDelay[7:0] \| Cycles to delay after refresh when the bank was previously dirty. Usually set to <code>54</code>, which is <code>tRETRYREFRESHDIRTY / 4</code>. \| 7-0 \| CleanRefreshDelay[7:0] \| Cycles to delay after refresh when the bank was previously clean. Usually set to <code>52</code>, which is <code>tRETRYREFRESHCLEAN / 4<code/>. Line 167: '''Extra Details:''' : The automatic refresh operation, when enabled, is triggered by VI's HSYNC timing. This forces the refresh operation to happen during HBLANK so it can't block VI's scanout. : As a single RDRAM's refresh command is refreshes 2 rows on all ~~bank~~banks, the standard NTSC/PAL video timings result in refreshing all 512 rows in 15.6ms or 16.4ms respectively, meeting the RDRAM spec of 17ms. : VI's HSYNC defaults to 41us on power-cycle. This results in a 10.5ms refresh cycle, ~~and~~causing a noticeable memory bandwidth reduction, until the VI is configured. ==== <span style="display:none;">0x0470 0014 - RI_LATENCY ====