RDRAM Interface: Difference between revisions

RDRAM Interface (view source)

Revision as of 22:03, 3 November 2023

607 bytes added , 6 months ago

RI_CONFIG and RI_CURRENT_LOAD: Relate fields to relevant RAC signals, document read behavior for RI_CURRENT_LOAD

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Tharo

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Revision as of 21:12, 3 November 2023 (view source) Tharo (talk \| contribs) (RI_ERROR: Mention that even if the OverRange error is flagged it does not inhibit RDRAM packets from being sent out) ← Older edit		Revision as of 22:03, 3 November 2023 (view source) Tharo (talk \| contribs) (RI_CONFIG and RI_CURRENT_LOAD: Relate fields to relevant RAC signals, document read behavior for RI_CURRENT_LOAD) Newer edit →
Line 65: <pre> READ?/WRITE: [6] Enable/Disable automatic current calibration from controller. Corresponds to the RAC CCtlEn input signal. It selects whether ~~the~~ the value CC[5:0] will be written to current control register (AutoCC=0), or if an internally generated value should be used (AutoCC=1). [5:0] Current Control Input. The value to be loaded into current control register when ~~autoCC~~AutoCC is disabled. Corresponds to the RAC CCtlI input signal. </pre> Line 93: <pre> WRITE: ~~TOVERIFY:~~ Any write to this register ~~will load~~causes a new value to be loaded into the RAC current control register. ~~The~~Corresponds ~~value loaded depends on~~to the ~~value of AutoCC. See~~RAC ~~RI_CONFIG~~CCtlLd ~~for~~input ~~details~~signal. The value loaded depends on the contents of the RI_CONFIG register, see there for details. TOVERIFY: When AutoCC=1 in RI_CONFIG and this register is written, a sufficient delay should be observed to let CC autocalibration stabilize. READ: This register is intended to be write-only, the read behavior is unintended and returns a collection of bits from other registers: [0] : RI_ERROR Ack [1] : 1 TOVERIFY always 1? [2] : 1 TOVERIFY always 1? [3] : RI_MODE STOP_R [4] : RI_SELECT TSEL[0] [32:5] : 0 TOVERIFY always 0? </pre>