RDRAM Interface: Difference between revisions

RDRAM Interface (view source)

125 bytes added , 6 months ago

RI_ERROR: Mention that even if the OverRange error is flagged it does not inhibit RDRAM packets from being sent out

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Revision as of 19:03, 3 November 2023 (view source) Tharo (talk \| contribs) (RI_BANK_STATUS: Further details) ← Older edit		Revision as of 21:12, 3 November 2023 (view source) Tharo (talk \| contribs) (RI_ERROR: Mention that even if the OverRange error is flagged it does not inhibit RDRAM packets from being sent out) Newer edit →
Line 197: \| U-? \|\| U-? \|\| U-? \|\| U-? \|\| U-? \|\| U-? \|\| U-? \|\| U-? \|- \| — \|\| — \|\| — \|\| — \|\| — \|\| — \|\| — \|\| — ~~\| colspan="8" \| DirtyRefreshDelay [7:0]~~ {{#invoke:Register table\|row\|7:0}} \| U-? \|\| U-? \|\| U-? \|\| U-? \|\| U-? \|\| R-? \|\| R-? \|\| R-? Line 205: {{#invoke:Register table\|definitions \| 31-3 \| Undefined \| Undefined \| 2 \| Over \| OverRangeError. Set when reading/writing any addresses in the range <code>0x0080 0000</code> to <code>0x03EF FFFF</code>, even ~~when~~if an RDRAM bank has been mapped there. However note that request packets are still sent out over the RDRAM bus even if this error was flagged. \| 1 \| NAck \| UnexpectedNAck. Set when RI sees an unexpected NAak (probably because bank status bits were wrong). \| 0 \| Ack \| MissingAck. Set when RI doesn't see an Ack (like when no RDRAM device was mapped to that address). <br>