RDRAM Interface: Difference between revisions
m
RI_REFRESH: MultiBank bitfield width is four bits.
(No idea what DmaLatencyOverlap does, but we do know it's 4 bits.) |
m (RI_REFRESH: MultiBank bitfield width is four bits.) |
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Line 133:
| U-? || U-? || U-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
{{#invoke:Register table|row|15:8}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
Line 145:
{{#invoke:Register table|definitions
| 31-?? | Undefined | Undefined
| ??-19| MultiBank[
| 18 | Opt | Optimize. Usually set to <code>0x1</code>.
| 17 | En | Enable. Usually set to <code>0x1</code>.
| |||