RDRAM Interface: Difference between revisions
Fill in RI_ERROR and RI_BANK_STATUS
(Add details about refresh timings) |
(Fill in RI_ERROR and RI_BANK_STATUS) |
||
Line 182:
}}
==== <span style="display:none;">0x0470 0018 - RI_ERROR ====
----
{{#invoke:Register table|head|550px|RI_ERROR <code>0x0470 0018</code>}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| colspan="8" | DirtyRefreshDelay [7:0]
{{#invoke:Register table|row|7:0}}
| U-? || U-? || U-? || U-? || U-? || R-? || R-? || R-?
|-
| — || — || — || — || — || OverRange || Ack ? || NAck ?
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-3 | Undefined | Undefined
| 2 | OverRange Error | Set when reading any addresses in the range <code>0x0080 0000</code> to <code>0x03EF FFFF</code>, even when an RDRAM bank has been mapped there.
| 1 | Ack Error? | ?
| 0 | NACK Error | Set when accessing an address with no mapped RDRAM device. This bit is set sometime during IPL3 init, presumably when probing memory size.
}}
Writing any value this register will clear any errors.
==== <span style="display:none;">0x0470 001c - RI_BANK_STATUS ====
----
{{#invoke:Register table|head|550px| RI_BANK_STATUS <code>0x0470 001c</code>}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
| colspan="8" | BankDirtyBits[7:0]
{{#invoke:Register table|row|7:0}}
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-?
|-
| colspan="8" | BankValidBits[7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-16 | ? |
| 15-8 | BankDirtyBits | One per bank. Set when a bank has been written since last refresh cycle
| 7-0 | BankValidBits | One per bank. Set when a bank has been read since last refresh cycle
}}
Writing any value this register will clear any tracking bits.
= Memory addressing =
| |||