RDRAM Interface: Difference between revisions
Add details about refresh timings
(Add details about refresh timings) |
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| 17 | En | Enable. Usually set to <code>0x1</code>.
| 16 | Bank | Usually set to <code>0x0</code>.
| 15-8 | DirtyRefreshDelay[7:0] | Cycles to delay after refresh when the bank was previously dirty. Usually set to <code>
| 7-0 | CleanRefreshDelay[7:0] | Cycles to delay after refresh when the bank was previously clean. Usually set to <code>
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'''Extra Details:'''
: The refresh operation is triggered by VI's HSYNC timing. This forces the refresh operation to happen during HBLANK so it can't block VI's scanout.
: As RDRAM's refresh command is refreshes 2 rows on all bank, the standard NTSC/PAL video timings result in refreshing all 512 rows in 15.6ms or 16.4ms, meeting the RDRAM spec of 17ms.
: VI's HSYNC defaults to 41us on power-cycle. This results in a 10.5ms refresh cycle, and a noticeable memory bandwidth reduction, until VI is configured.
==== <span style="display:none;">0x0470 0014 - RI_LATENCY ====
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