RDRAM Interface: Difference between revisions
Add RI_REFRESH description
(Add RI_REFRESH description) |
|||
Line 121:
}}
==== <span style="display:none;">0x0470 0010 - RI_REFRESH ====
----
{{#invoke:Register table|head|550px|RI_REFRESH <code>0x0470 0010</code>}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-? || U-? || U-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
| — || — || — || colspan="2" | MultiBank[??:0] || Opt || En || Bank
{{#invoke:Register table|row|15:8}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
| colspan="8" | DirtyRefreshDelay [7:0]
{{#invoke:Register table|row|7:0}}
| RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-? || RW-?
|-
| colspan="8" | CleanRefreshDelay [7:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-?? | Undefined | Undefined
| ??-19| MultiBank[??:0] | Bitfield indicating multibanks rdram modules. (Bitfield size to be determined, very likely between 2 and 8). <br>Probably why RDRAM modules are re-ordered with multibanks modules first.
| 18 | Opt | Optimize. Usually set to <code>0x1</code>.
| 17 | En | Enable. Usually set to <code>0x1</code>.
| 16 | Bank | Usually set to <code>0x0</code>.
| 15-8 | DirtyRefreshDelay[7:0] | Usually set to <code>0x36</code>.
| 7-0 | CleanRefreshDelay[7:0] | Usually set to <code>0x34</code>.
}}
TODO: remaining registers
| |||