RDRAM Interface: Difference between revisions
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Fixed header and minor formatting. Added SMode packet source.
(Cleaned formatting and added content to RI_MODE register.) |
m (Fixed header and minor formatting. Added SMode packet source.) |
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| 3 | STOP_R | Automatic halting of RAC clock used for receive logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled
| 2 | STOP_T | Automatic halting of RAC clock used for transmit logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled
| 1-0 | OP_MODE[1:0] | Controls how Serial Mode (SMode) packets are sent to RDRAM modules. [http://www.bitsavers.org/components/nec/_dataBooks/1995_NEC_Application_Specific_Memory.pdf] Usually set to <code>10</code>. <br>11 {{=}} Unknown <br>10 {{=}} Sends a packet before each RDRAM transaction. Tells the modules to enter standby mode after receiving each transaction. <br>01 {{=}} Sends a packet every 4 BusClk cycles. Tells the modules to always be active (consumes more power and usually not used). <br>00 {{=}} Sends continuous packets. After 272 BusClk cycles, all RDRAM modules will enter a reset mode. <br>{{spaces|4}}<i>Due to the timing differences, some changes will require a delay to become active.</i>
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TODO: remaining registers
RI translate memory accesses in the range <code>0x0000 0000</code> - <code>0x03FF FFFF</code> into suitable RDRAM protocol packets with proper command type and 36 bit address. See [[RDRAM|RDRAM addressing]] paragraph for details about how 36bit addresses are interpreted.
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