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RDRAM Interface: Difference between revisions

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RDRAM Interface (view source)

Revision as of 00:42, 2 September 2021

66 bytes added ,  2 years ago
Cleaned formatting and added content to RI_MODE register.
VisualWikitext
(Verified the RI contains a RAC, and clarified which specific registers were defined on this page.)
(Cleaned formatting and added content to RI_MODE register.)
Line 11:
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at power onboot
-? = Unknown default value
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0470 0000 - RI_MODE ====
----
{{#invoke:Register table|head|550px600px|RI_MODE <code>0x0470 0000</code>}}
{{#invoke:Register table|row|31:24}}
| U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0 || U-?0
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-?0 || U-?0 || U-?0 || U-?0 || RW-?1 || RW-?1 || RW-? || RW-?
|-
| — || — || — || — || Stop_RSTOP_R || Stop_TSTOP_T || colspan="2" | Op_Mode OP_MODE[1:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
<pre>
| 31-4 | Undefined | Initialized to <code>0</code>
READ/WRITE:
| 3 | STOP_R | Automatic halting of RAC clock used for receive logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled
[3] Enable/Disable controller Receive clock automatic stopping.
| 2 | STOP_T | Automatic halting of RAC clock used for transmit logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled
[2] Enable/Disable controller Transmit clock automatic stopping.
| 1-0 | OP_MODE[1:0] | Controls how Serial Mode (SMode) packets are sent to RDRAM modules. Usually set to <code>10</code>. <br>11 {{=}} Unknown <br>10 {{=}} Sends a packet before each RDRAM transaction. Tells the modules to enter standby mode after receiving each transaction. <br>01 {{=}} Sends a packet every 4 BusClk cycles. Tells the modules to always be active (consumes more power and usually not used). <br>00 {{=}} Sends continuous packets. After 272 BusClk cycles, all RDRAM modules will enter a reset mode. <br><i>Due to the timing differences, some changes will require a delay to become active.</i>
[1:0] Operating mode of RDRAM modules (not sure if it is the operating mode of the controller, if it makes the controller forward orders to place RDRAM modules in these states).
}}
0: Reset. place device in known state after poweron.
1: Active. device is active and ready to receive requests. This mode consumes the most power and is not used directly.
2: Standby. device automatically transition to this state after servicing a transaction. This is the default operating mode.
NOTE: some RDRAM datasheets mention a 4th mode PowerDown, but I'm not sure it is supported in N64 configuration.
NOTE: transition between these states takes several cycles, so after setting them some delay is necessary for them to be effective.
</pre>
 
 
==== <span style="display:none;">0x0470 0004 - RI_CONFIG ====
----
{{#invoke:Register table|head|550px600px|RI_CONFIG <code>0x0470 0004</code>}}
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
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