Revision as of 21:08, 31 August 2021 (view source) Bsmiles32 (talk \| contribs) (RI translation does very likely "disable" address swapping for registers operations by duplicating content between Adr[28:20] and Adr[19:11]) Tag: Visual edit ← Older edit		Revision as of 22:00, 31 August 2021 (view source) Bsmiles32 (talk \| contribs) (Add link to some RAC datasheet) Tag: Visual edit Newer edit →
Line 1: The RDRAM Interface (or '''RI''') act as a controller of the RDRAM channel to which one or more RDRAM modules are ~~daisy-chained~~connected. It converts memory accesses from the system into RDRAM protocol commands, to which RDRAM modules responds. The RI very likely integrates a RDRAM ASIC Cell (or '''RAC''') in order to take care of the low level details of the RDRAM bus. Further details which helps better understanding the RI can be found in datasheets of such RAC like [https://www.datasheetarchive.com/pdf/download.php?id=04f8a219efa5e2304d0e403c3f77e759adedf8&type=O&term=rac%2520rdram this one] (even if it may not be the very same version used in the official RI). The memory area devoted to RDRAM Interface and RDRAM modules is divided as follow :

RDRAM Interface: Difference between revisions

RDRAM Interface (view source)