RDRAM Interface: Difference between revisions
RI_BANK_STATUS: Further details
m (RI_REFRESH: MultiBank bitfield width is four bits.) |
(RI_BANK_STATUS: Further details) |
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{{#invoke:Register table|definitions
| 31-16 | Undefined | Undefined
| 15-8 | BankDirtyBits[7:0] | One per bank. Set when the currently open row has been written. Cleared when a new row is opened but not yet written to.
| 7-0 | BankValidBits[7:0] | One per bank. Set when a row is opened. Presumably only cleared by a refresh cycle.
}}
Writing any value to this register will
Memory read/write requests to banks mapped above 8MiB do not update any of these bits. This may also cause out-of-sync errors as the RI appears to be unable to track the current open row state for banks above 8MiB.
'''Note:''' Some sources such as libultra's <code>rcp.h</code> header call this register <code>RI_WERROR</code>, however this register is unrelated to errors. The name <code>RI_BANK_STATUS</code> comes from a patent and is much more descriptive of the function of this register.
= Memory addressing =
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