RDRAM Interface: Difference between revisions
Cleaned formatting and added content to RI_MODE register.
(Verified the RI contains a RAC, and clarified which specific registers were defined on this page.) |
(Cleaned formatting and added content to RI_MODE register.) |
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Line 11:
W = Writable bit
U = Undefined/Unused bit
-n = Default value n at
-? = Unknown default value
[x:y] = Specifies bits x to y, inclusively</pre>
==== <span style="display:none;">0x0470 0000 - RI_MODE ====
----
{{#invoke:Register table|head|
{{#invoke:Register table|row|31:24}}
| U-
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| U-
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| U-
|-
| — || — || — || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| U-
|-
| — || — || — || — ||
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31-4 | Undefined | Initialized to <code>0</code>
| 3 | STOP_R | Automatic halting of RAC clock used for receive logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled
| 2 | STOP_T | Automatic halting of RAC clock used for transmit logic when not in use, normally enabled. <br>1 {{=}} Enabled <br>0 {{=}} Disabled
| 1-0 | OP_MODE[1:0] | Controls how Serial Mode (SMode) packets are sent to RDRAM modules. Usually set to <code>10</code>. <br>11 {{=}} Unknown <br>10 {{=}} Sends a packet before each RDRAM transaction. Tells the modules to enter standby mode after receiving each transaction. <br>01 {{=}} Sends a packet every 4 BusClk cycles. Tells the modules to always be active (consumes more power and usually not used). <br>00 {{=}} Sends continuous packets. After 272 BusClk cycles, all RDRAM modules will enter a reset mode. <br><i>Due to the timing differences, some changes will require a delay to become active.</i>
}}
==== <span style="display:none;">0x0470 0004 - RI_CONFIG ====
----
{{#invoke:Register table|head|
{{#invoke:Register table|row|31:24}}
| U-? || U-? || U-? || U-? || U-? || U-? || U-? || U-?
|