RDRAM: Difference between revisions
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m (fix copypasta) |
(Change register section headings, as MediaWiki really hates linking to anchors with square brackets in them.) |
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TODO: detailed register description, with bit layout and arrows. |
TODO: detailed register description, with bit layout and arrows. |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x00 - DeviceType ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|DeviceType <code>0x00</code>}} |
{{#invoke:Register table|head|600px|DeviceType <code>0x00</code>}} |
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}} |
}} |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x01 - DeviceId ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|DeviceId <code>0x01</code>}} |
{{#invoke:Register table|head|600px|DeviceId <code>0x01</code>}} |
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}} |
}} |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x02 - Delay ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|Delay <code>0x02</code>}} |
{{#invoke:Register table|head|600px|Delay <code>0x02</code>}} |
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''<sup>[1]</sup> The Toshiba 8Mbit datasheet confirms this as the default. It default to 4, because some devices (like the Toshiba 18Mbit) only have 2 bits, so can only support a maximum write delay of 4. Devices with more bits default to 0b100 for compatibility.'' |
''<sup>[1]</sup> The Toshiba 8Mbit datasheet confirms this as the default. It default to 4, because some devices (like the Toshiba 18Mbit) only have 2 bits, so can only support a maximum write delay of 4. Devices with more bits default to 0b100 for compatibility.'' |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x03 - Mode ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|Mode <code>0x03</code>}} |
{{#invoke:Register table|head|600px|Mode <code>0x03</code>}} |
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}} |
}} |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x04 - RefInterval ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|RefInterval <code>0x04</code>}} |
{{#invoke:Register table|head|600px|RefInterval <code>0x04</code>}} |
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}} |
}} |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x05 - RefRow ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|RefRow <code>0x05</code>}} |
{{#invoke:Register table|head|600px|RefRow <code>0x05</code>}} |
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This register is normally read or written only for testing purpose. |
This register is normally read or written only for testing purpose. |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x06 - RasInterval ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|RasInterval <code>0x06</code>}} |
{{#invoke:Register table|head|600px|RasInterval <code>0x06</code>}} |
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NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB). |
NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB). |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x07 - MinInterval ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px|MinInterval <code>0x07</code>}} |
{{#invoke:Register table|head|600px|MinInterval <code>0x07</code>}} |
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''The N64 implements refresh by broadcasting one SetRR command whenever VI emits a horizontal sync pulse.'' |
''The N64 implements refresh by broadcasting one SetRR command whenever VI emits a horizontal sync pulse.'' |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x08 - AddressSelect ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px| AddressSelect <code>0x08</code>}} |
{{#invoke:Register table|head|600px| AddressSelect <code>0x08</code>}} |
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: However, RI doesn't appear to support this feature. It expects Bank zero to be in the first megabyte of address space, Bank one in the second megabyte, and so on. |
: However, RI doesn't appear to support this feature. It expects Bank zero to be in the first megabyte of address space, Bank one in the second megabyte, and so on. |
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==== <span style="display:none;"> |
==== <span style="display:none;">0x09 - DeviceManufacturer ==== |
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---- |
---- |
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{{#invoke:Register table|head|600px| DeviceManufacturer <code>0x09</code>}} |
{{#invoke:Register table|head|600px| DeviceManufacturer <code>0x09</code>}} |
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