RDRAM: Difference between revisions

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m (Clarify that MI_MODE_REG = 0x10f is a prerequisite for RDRAM delay configuration and what should be written where)
(Add MinInterval Register description)
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NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB).
NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB).

==== <span style="display:none;">AdrS[9:2] 0x07 - MinInterval ====
----
{{#invoke:Register table|head|600px|MinInterval <code>0x07</code>}}
{{#invoke:Register table|row|31:24}}
| R-0 || R-0 || R-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| MAD[3] || MRD[3] || MWD[3] || — || — || — || — || —
{{#invoke:Register table|row|23:16}}
| R-0 || R-1 || R-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| MAD[2] || MRD[2] || MWD[2] || — || — || — || — || —
{{#invoke:Register table|row|15:8}}
| R-1 || R-1 || R-0 || U-0 || U-0 || U-0 || U-0 || U-0
|-
| MAD[1] || MRD[1] || MWD[1] || — || — || — || — || —
{{#invoke:Register table|row|7:0}}
| R-1 || R-1 || R-1 || W-? || W-? || W-? || W-? || W-?
|-
| MAD[0] || MRD[0] || MWD[0] || colspan="5" | SpecFunc[4:0]
{{#invoke:Register table|foot}}
{{#invoke:Register table|definitions
| 31,23,15,7 | MinAckDelay | Minimum of AckDelay of RDRAM.
| 30,22,14,6 | MinReadDelay | Minimum of ReadDelay of RDRAM.
| 29,21,13,5 | MinWriteDelay | Minimum of WriteDelay of RDRAM.
| 4-0 | SpecFunc | Performs SetRR burst refresh and SetPD powerdown entry.
}}


= RDRAM addressing =
= RDRAM addressing =