RDRAM: Difference between revisions
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m (Clarify that MI_MODE_REG = 0x10f is a prerequisite for RDRAM delay configuration and what should be written where) |
(Add MinInterval Register description) |
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NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB). |
NOTE: all fields are in bit reversed order (bit 4 is LSB, bit 0 is MSB). |
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==== <span style="display:none;">AdrS[9:2] 0x07 - MinInterval ==== |
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---- |
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{{#invoke:Register table|head|600px|MinInterval <code>0x07</code>}} |
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{{#invoke:Register table|row|31:24}} |
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| R-0 || R-0 || R-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
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| MAD[3] || MRD[3] || MWD[3] || — || — || — || — || — |
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{{#invoke:Register table|row|23:16}} |
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| R-0 || R-1 || R-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
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| MAD[2] || MRD[2] || MWD[2] || — || — || — || — || — |
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{{#invoke:Register table|row|15:8}} |
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| R-1 || R-1 || R-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
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| MAD[1] || MRD[1] || MWD[1] || — || — || — || — || — |
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{{#invoke:Register table|row|7:0}} |
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| R-1 || R-1 || R-1 || W-? || W-? || W-? || W-? || W-? |
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|- |
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| MAD[0] || MRD[0] || MWD[0] || colspan="5" | SpecFunc[4:0] |
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{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
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| 31,23,15,7 | MinAckDelay | Minimum of AckDelay of RDRAM. |
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| 30,22,14,6 | MinReadDelay | Minimum of ReadDelay of RDRAM. |
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| 29,21,13,5 | MinWriteDelay | Minimum of WriteDelay of RDRAM. |
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| 4-0 | SpecFunc | Performs SetRR burst refresh and SetPD powerdown entry. |
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}} |
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= RDRAM addressing = |
= RDRAM addressing = |