RDRAM: Difference between revisions
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(Fix bits ordering in RDRAM registers layout.) |
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Programming caution : |
Programming caution : |
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* RDRAM registers are '''little-endian'''. The RI does not perform any endian-swap, so the value that is read or written by the CPU '''must be endian-swapped''' to match the register layout described in this page. |
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* Before reading any RDRAM register content, RDRAM current control must be calibrated |
* Before reading any RDRAM register content, RDRAM current control must be calibrated |
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* Also, it seems that RDRAM register reads should be surrounded by MI_MODE = SET_DRAM_REG / CLR_DRAM_REG |
* Also, it seems that RDRAM register reads should be surrounded by MI_MODE = SET_DRAM_REG / CLR_DRAM_REG |
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{{#invoke:Register table|head|600px|DeviceType <code>0x00</code>}} |
{{#invoke:Register table|head|600px|DeviceType <code>0x00</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| R- |
| R-? || R-? || R-? || R-? || U-0 || R-1 || U-0 || R-? |
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|- |
|- |
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| colspan="4" | |
| colspan="4" | ColumnBits || — || Bn || — || En |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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⚫ | |||
⚫ | |||
⚫ | |||
⚫ | |||
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-? |
| R-? || R-? || R-? || R-? || R-? || R-? || R-? || R-? |
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|- |
|- |
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| colspan="4" | BankBits || colspan="4" | RowBits |
| colspan="4" | BankBits || colspan="4" | RowBits |
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⚫ | |||
⚫ | |||
⚫ | |||
⚫ | |||
{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| R- |
| R-0 || R-0 || R-0 || R-? || R-0 || R-0 || R-0 || R-0 |
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|- |
|- |
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| colspan="4" | |
| colspan="4" | Version || colspan="4" | Type |
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{{#invoke:Register table|foot}} |
{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
{{#invoke:Register table|definitions |
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⚫ | |||
| 31-28 | Version | RDRAM version. <br>0001 {{=}} Extended architecture (Base RDRAM protocol) |
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| 26 | Bn | Bonus, number of bits per byte. <br>0 {{=}} 8bit byte<br>1 {{=}} 9bit byte |
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| 24 | En | Enhanced speed grade. <br>0 {{=}} Normal<br> 1 {{=}} Low Latency |
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⚫ | |||
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| 23-20 | BankBits | Number of bank address bits, or said differently, declares that this RDRAM device has 2^BankBits banks. |
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| 19-16 | RowBits | Number of row address bits, or said differently, declares that this RDRAM devices has 2^RowBits rows per bank. |
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| |
| 7-4 | Version | RDRAM version. <br>0001 {{=}} Extended architecture (Base RDRAM protocol) |
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| 0 | |
| 3-0 | Type | Device type. <br>0000 {{=}} RDRAM device |
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}} |
}} |
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{{#invoke:Register table|head|600px|DeviceId <code>0x01</code>}} |
{{#invoke:Register table|head|600px|DeviceId <code>0x01</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| RW-0 || |
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| IdField[ |
| colspan="5" | IdField[25:20] || — || — || — |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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⚫ | |||
⚫ | |||
⚫ | |||
⚫ | |||
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 |
| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || RW-0 |
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|- |
|- |
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| colspan="8" | IdField[34:27] |
| colspan="8" | IdField[34:27] |
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{{#invoke:Register table|row| |
{{#invoke:Register table|row|7:0}} |
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| RW-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
| RW-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| IdField[ |
| IdField[35] || — || — || — || — || — || — || — |
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{{#invoke:Register table|row|7:0}} |
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| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0 |
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⚫ | |||
| colspan="5" | IdField[25:20] || — || — || — |
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{{#invoke:Register table|foot}} |
{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
{{#invoke:Register table|definitions |
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| |
| 7,15-8,23,31-26 | IdField[35:k] | Compared to AdrS[35:k] to select RDRAM.<br>k {{=}} 21 for 16/18Mbit RDRAM.<br>k {{=}} 20 for 8/9Mbit RDRAM. |
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}} |
}} |
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{{#invoke:Register table|head|600px|Mode <code>0x03</code>}} |
{{#invoke:Register table|head|600px|Mode <code>0x03</code>}} |
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{{#invoke:Register table|row|31:24}} |
{{#invoke:Register table|row|31:24}} |
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| RW-1 || RW-1 || |
| RW-1 || RW-1 || RW-0 || R-0 || RW-0 || RW-1 || RW-0 || RW-0 |
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|- |
|- |
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| |
| CE || X2 || PL || SV || SK || AS || DE || LE |
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{{#invoke:Register table|row|23:16}} |
{{#invoke:Register table|row|23:16}} |
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⚫ | |||
⚫ | |||
⚫ | |||
⚫ | |||
| RW-1 || RW-1 || U-0 || U-0 || RW-0 || U-0 || U-0 || U-0 |
| RW-1 || RW-1 || U-0 || U-0 || RW-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| C5 || C2 || — || — || AD || — || — || — |
| C5 || C2 || — || — || AD || — || — || — |
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⚫ | |||
⚫ | |||
⚫ | |||
| C4 || C1 || — || — || — || — || — || — |
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{{#invoke:Register table|row|7:0}} |
{{#invoke:Register table|row|7:0}} |
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| RW-1 || RW-1 || |
| RW-1 || RW-1 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 |
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|- |
|- |
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| |
| C3 || C0 || — || — || — || — || — || — |
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{{#invoke:Register table|foot}} |
{{#invoke:Register table|foot}} |
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{{#invoke:Register table|definitions |
{{#invoke:Register table|definitions |
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⚫ | |||
⚫ | | |
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⚫ | |||
⚫ | |||
| 29 | PL | Select PowerDown Latency |
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⚫ | |||
⚫ | |||
⚫ | |||
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| 27 | SK / Skip| For tests. 0 |
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| 26 | AS / AutoSkip | For tests. 1 |
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⚫ | |||
⚫ | |||
⚫ | |||
| 2 | AS / AutoSkip | For tests. 1 |
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⚫ | |||
⚫ | |||
⚫ | | 23,15,7,22,14,6 | C[5:0] / CCValue | Current Control value which controls ''in fine'' the output current I<sub>OL</sub>.<br>In manual mode (CE{{=}}0), I<sub>OL</sub> is proportional to (63-CC) with I<sub>OL</sub> ~ (0.95±0.3)×(63-CC) mA, for CC {{=}} 0..63. (These coefficients derive from Imax±△/63 and vary between models)<br>This field is inverted when read.<br>In auto mode (CE{{=}}1), I<sub>OL</sub> is proportional to (63-CC) with I<sub>OL</sub> ~ (1.25±0.1)×(63-CC) mA, for CC {{=}} 31..63. (These coefficients derive from I<sub>40</sub>±△/(63-31) and vary between models)<br>An internally generated value is returned when read. |
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⚫ | |||
}} |
}} |
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