RDRAM: Difference between revisions

RDRAM Initialization procedure as implemented in IPL3:

1. a. Enable RI Auto Current

b. let it settle by waiting using countdown(8800)

c. load RI CC value

2. Enable RI T/R select

3. a. Force RI_MODE reset, disable R/T stop

b. wait using countdown(4)

4. a. Force RI_MODE standby, enable R/T stop

b. wait using countdown(32)

5. Set MI INIT mode + length=15

6. a. Setup all RDRAM delays (AckWin=11,Read=9,Ack=3,Write=7) [bcast]

b. Setup all RDRAM refresh row to 0 [bcast]

c. Move all RDRAM modules to top of address space deviceid = 0x80000000 [bcast]

7. a. compute rdram reg space size (reg_step) based on RCP version (RCPv1: 128, RCPv2: 256)

b. init top rdram reg pointer (RDRAM_REGS_BASE + 32 * reg_step)

8. First pass which walk through at most 8 RDRAMs and for valid ones:

a. place them at next 2MB boundary (eg. rdram_deviceid = i * 0x08000000)

b. compute optimal (auto) current calibration value for RDRAM module and apply it

c. exit first pass loop if cc value is zero, eg. no RDRAM module is present

d. read device description registers (device_type + manufaturer). These reads must be surrounded by MI_MODE= SET_DRAM_REG and CLR_DRAM_REG because individual rdram registers are accessed.

e. based on device description, setup optimal RAS timing

f. store RDRAM parameters (CC, geometry {eg. col, bank, row fields from device_type}) for second pass

g. update values which tracks how to reorder all 2MB RDRAM modules before the 1MB, how many modules are effectively presents and the 2MB_bitfield (=2^(number of 2MB modules)-1, because all 2MB banks will be placed first)

9. a. Disable all RDRAM modules (rdram_mode = 0xc4000000) [bcast]

b. and move them all back to top of address space (rdram_deviceid = 0x80000000) [bcast]

10. Second pass iterate through all modules discovered during the first pass and:

a. reorder them so that all 2MB modules are placed before 1MB modules

b. write previously computed optimal CC for each module

c. touch RDRAM modules to settle their timing circuits.

1MB modules undergo 4 consecutive reads (ptr+k*0x00080000, k=0..1) x 2

2MB modules undergo 8 consecutive reads (ptr+k*0x00080000, k=0..3) x 2

11. a. setup RI refresh register = 0x63634 | 2MB_bitfield << 19

b. do a dummy read of RI refresh reg

12. Return amount of detected RDRAM.

Trivia: there is very likely a copy-paste error in the original IPL3 code when incrementing t6 in the second pass. It should have been t8 so we can place next 1MB module at next slot. But I guess it went unnoticed because retail models don't use 1MB modules.