RDRAM: Difference between revisions

==== <span style="display:none;">AdrS[9:2] 0x02 - Delay ====

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{{#invoke:Register table|head|600px|Delay <code>0x02</code>}}

{{#invoke:Register table|row|31:24}}

| U-0 || U-0 || RW-? || RW-? || RW-? || R-0 || R-1 || R-1

|-

| — || — || colspan="3" | AckWinDelay || colspan="3" | AckWinBits

{{#invoke:Register table|row|23:16}}

| U-0 || U-0 || RW-? || RW-? || RW-? || R-0 || R-1 || R-1

|-

| — || — || colspan="3" | ReadDelay || colspan="3" | ReadBits

{{#invoke:Register table|row|15:8}}

| U-0 || U-0 || U-0 || RW-? || RW-? || R-0 || R-1 || R-0

|-

| — || — || — || colspan="2" | AckDelay || colspan="3" | AckBits

{{#invoke:Register table|row|7:0}}

| U-0 || U-0 || RW-? || RW-? || RW-? || R-0 || R-1 || R-1

|-

| — || — || colspan="3" | WriteDelay || colspan="3" | WriteBits

{{#invoke:Register table|foot}}

{{#invoke:Register table|definitions

| 29-27 | AckWinDelay[2:0] | Adjusts the size of the acknowledge window. Normally set to 5.

| 26-24 | AckWinBits[2:0] | Read-only. Number of bits of AckWinDelay (3).

| 21-19 | ReadDelay[2:0] | Delay between end of request and start of Read data packet. Normally set to 7.

| 18-16 | ReadBits[2:0] | Read-only. Number of bits of ReadDelay (3).

| 12-11 | AckDelay[1:0] | Delay between end of request and start of Ack data packet. Normally set to 3.

| 10-8 | AckBits[2:0] | Read-only. Number of bits of AckDelay (2).

| 5-3 | WriteDelay[2:0] | Delay between end of request and start of Write data packet. Normally set to 1.

| 2-0 | WriteBits[2:0] | Read-only. Number of bits of WriteDelay (3).

}}

NOTE: IPL3 set this register to 0x18082838 (AckWin = 3, Read = 1, Ack = 5, Write = 7), which doesn't match the recommended values. Recommended value would be 0x28381808. Also, Ack value set by IPL3 (5) doesn't fit in AckDelay field (only 2 bits)... So there must be something wrong in either IPL3 or the current description.