RDRAM: Difference between revisions

* RDRAM registers are '''little-endian'''. The RI does not perform any endian-swap, so the value that is read or written by the CPU '''must be endian-swapped''' to match the register layout described in this page.

| R-0 || R-0 || R-0 || R-? || R-0 || R-0 || R-0 || R-0

| colspan="4" | Version || colspan="4" | Type

| U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0

|-

| — || — || — || — || — || — || — || —

{{#invoke:Register table|row|15:8}}

| R-? || R-? || R-? || R-? || U-0 || R-1 || U-0 || R-?

| colspan="4" | ColumnBits || — || Bn || — || En

| 31-28 | Version | RDRAM version. <br>0001 {{=}} Extended architecture (Base RDRAM protocol)

| 27-24 | Type | Device type. <br>0000 {{=}} RDRAM device

| 15-12 | BankBits | Number of bank address bits, or said differently, declares that this RDRAM device has 2^BankBits banks.

| 11-8 | RowBits | Number of row address bits, or said differently, declares that this RDRAM devices has 2^RowBits rows per bank.

| 7-4 | ColumnBits | Number of column address bits, or said differently, declares that this RDRAM device has 2^ColumnBits bytes per row.

| 2 | Bn | Bonus, number of bits per byte. <br>0 {{=}} 8bit byte<br>1 {{=}} 9bit byte

| 0 | En | Enhanced speed grade. <br>0 {{=}} Normal<br> 1 {{=}} Low Latency

| RW-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0

| IdField[35] || — || — || — || — || — || — || —

{{#invoke:Register table|row|15:8}}

| IdField[26] || — || — || — || — || — || — || —

{{#invoke:Register table|row|7:0}}

| RW-0 || RW-0 || RW-0 || RW-0 || RW-0 || U-0 || U-0 || U-0

|-

| colspan="5" | IdField[25:20] || — || — || —

| 31,23-16,15,7-3 | IdField[35:k] | Compared to AdrS[35:k] to select RDRAM.<br>k {{=}} 21 for 16/18Mbit RDRAM.<br>k {{=}} 20 for 8/9Mbit RDRAM.

| RW-1 || RW-1 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0

| C3 || C0 || — || — || — || — || — || —

| RW-1 || RW-1 || U-0 || U-0 || U-0 || U-0 || U-0 || U-0

|-

| C4 || C1 || — || — || — || — || — || —

{{#invoke:Register table|row|15:8}}

| RW-1 || RW-1 || RW-0 || R-0 || RW-0 || RW-1 || RW-0 || RW-0

| CE || X2 || PL || SV || SK || AS || DE || LE

| 15,23,31,14,22,30 | C[5:0] / CCValue | Current Control value which controls ''in fine'' the output current I_OL.<br>In manual mode (CE{{=}}0), I_OL is proportional to (63-CC) with I_OL ~ (0.95±0.3)×(63-CC) mA, for CC {{=}} 0..63. (These coefficients derive from Imax±△/63 and vary between models)<br>This field is inverted when read.<br>In auto mode (CE{{=}}1), I_OL is proportional to (63-CC) with I_OL ~ (1.25±0.1)×(63-CC) mA, for CC {{=}} 31..63. (These coefficients derive from I₄₀±△/(63-31) and vary between models)<br>An internally generated value is returned when read.

| 11 | AD / AckDis | For low latency RDRAM only. Allows to supress acknowledge response when set to 1.

| 7 | CE / CCEnable| Current Control Enable.<br>0 {{=}} manual<br>1 {{=}} auto

| 6 | X2 / CCMult | Should be 1. Inverted when read. (Toshiba datasheet states that it select wether X₁ or X₂ register is used for the current control register).

| 5 | PL | Select PowerDown Latency

| 4 | SV / SkipValue | For tests. 0

| 3 | SK / Skip| For tests. 0

| 2 | AS / AutoSkip | For tests. 1

| 1 | DE / DeviceEnable | Enable RDRAM device. When disabled, only broadcast register requests can be executed.<br>0 {{=}} disabled<br>1 {{=}} enabled

| 0 | LE | Enable PowerDown mode for RDRAM that supports it to reduce power consumption.